参数资料
型号: SC470ITSTRT
厂商: Semtech
文件页数: 20/31页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 14-TSSOP
标准包装: 1
PWM 型: 控制器
输出数: 1
电源电压: 5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
包装: 标准包装
产品目录页面: 1358 (CN2011-ZH PDF)
其它名称: SC470ITSDKR
NOT RECOMMENDED FOR NEW DESIGN
SC470
POWER MANAGEMENT
Application Information (Cont.)
Figure 13: Power Component Placement and Copper Pours
Key points for the power section:
1) There should be a very small input loop, well decoupled.
2) The phase node should be a large copper pour, but compact since this is the noisiest node.
3) Input power ground and output power ground should not connect directly, but through the ground planes instead.
4) Notice in Figure 10 on page 18, the placement of 0 ? resistor at the bottom of the output capacitor to connect
to VSSA.
5) The current limit resistor should be placed as close as possible to the ILIM and LX pins.
Connecting the control and power sections should be accomplished as follows (see Figure 14 on Page 21):
1) Route VSSA and VOUT as differential pairs routed in a “quiet” layer away from noise sources.
2) Route DL, DH and LX (low-side FET gate drive, high side FET gate drive and phase node) to chip using wide traces
with multiple vias if using more than one layer. These connections to be as short as possible for loop minimization,
with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power
ground as its return path. LX is the noisiest node in the circuit, switching between V BAT and ground at high frequencies,
thus should be kept as short as practical. DH has LX as its return path.
3) BST is also a noisy node and should be kept as short as possible.
4) Connect PGND pin on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the ground
plane.
? 2005 Semtech Corp.
20
www.semtech.com
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