![](http://datasheet.mmic.net.cn/30000/MC9S12XF512J0VLHR_datasheet_2373534/MC9S12XF512J0VLHR_793.png)
Chapter 16 S12X Debug (S12XDBGV3) Module
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
793
CPU12X Information Byte
CXINF Information Byte
This describes the format of the information byte used only when tracing from CPU12X or XGATE in
Detail Mode. When tracing from the CPU12X in Detail Mode, information is stored to the trace buffer on
all cycles except opcode fetch and free cycles. The XGATE entry stored on the same line is a snapshot of
the XGATE program counter. In this case the CSZ and CRW bits indicate the type of access being made
by the CPU12X, whilst the XACK and XOCF bits indicate if the simultaneous XGATE cycle is a free cycle
(no bus acknowledge) or opcode fetch cycle. Similarly when tracing from the XGATE in Detail Mode,
information is stored to the trace buffer on all cycles except opcode fetch and free cycles. The CPU12X
entry stored on the same line is a snapshot of the CPU12X program counter. In this case the XSZ and XRW
bits indicate the type of access being made by the XGATE, whilst the CFREE and COCF bits indicate if
the simultaneous CPU12X cycle is a free cycle or opcode fetch cycle.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CSD
CVA
0
CDV
0
Figure 16-25. CPU12X Information Byte CINF
Table 16-44. CINF Field Descriptions
Field
Description
7
CSD
Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination
address. This is only used in Normal and Loop1 mode tracing.
0 Source address
1 Destination address
6
CVA
Vector Indicator — This bit indicates if the corresponding stored address is a vector address.. Vector addresses
are destination addresses, thus if CVA is set, then the corresponding CSD is also set. This is only used in Normal
and Loop1 mode tracing. This bit has no meaning in Pure PC mode.
0 Indexed jump destination address
1 Vector destination address
4
CDV
Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from
both sources in Normal, Loop1 and Pure PC modes, to indicate that the CPU12X trace buffer entry is valid.
0 Trace buffer entry is invalid
1 Trace buffer entry is valid
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CFREE
CSZ
CRW
COCF
XACK
XSZ
XRW
XOCF
Figure 16-26. Information Byte CXINF
Table 16-45. CXINF Field Descriptions
Field
Description
7
CFREE
CPU12X Free Cycle Indicator — This bit indicates if the stored CPU12X address corresponds to a free cycle.
This bit only contains valid information when tracing the XGATE accesses in Detail Mode.
0 Stored information corresponds to free cycle
1 Stored information does not correspond to free cycle