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Chapter 22 Enhanced Programmable Interrupt Timer (S12XEPIT24B8CV1)
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
1017
22.4.0.1
PIT Control and Force Load Micro Timer Register (PITCFLMT)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
22.4.0.2
PIT Force Load Timer Register (PITFLT)
Read: Anytime
Write: Anytime
Module Base + 0x0000
76543210
R
PITE
PITSWAI
PITFRZ
00000
W
PITFLMT1
PITFLMT0
Reset
0
00000
= Unimplemented or Reserved
Figure 22-3. PIT Control and Force Load Micro Timer Register (PITCFLMT)
Table 22-1. PITCFLMT Field Descriptions
Field
Description
7
PITE
PIT Module Enable Bit — This bit enables the PIT module. If PITE is cleared, the PIT module is disabled and
ag bits in the PITTF register are cleared. When PITE is set, individually enabled timers (PCE set) start down-
counting with the corresponding load register values.
0 PIT disabled (lower power consumption).
1 PIT is enabled.
6
PITSWAI
PIT Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.
0 PIT operates normally in wait mode
1 PIT clock generation stops and freezes the PIT module when in wait mode
5
PITFRZ
PIT Counter Freeze while in Freeze Mode Bit — When during debugging a breakpoint (freeze mode) is
encountered it is useful in many cases to freeze the PIT counters to avoid e.g. interrupt generation. The PITFRZ
bit controls the PIT operation while in freeze mode.
0 PIT operates normally in freeze mode
1 PIT counters are stalled when in freeze mode
1:0
PITFLMT
[1:0]
PIT Force Load Bits for Micro Timer 1:0 — These bits have only an effect if the corresponding micro timer is
active and if the PIT module is enabled (PITE set). Writing a one into a PITFLMT bit loads the corresponding 8-
bit micro timer load register into the 8-bit micro timer down-counter. Writing a zero has no effect. Reading these
bits will always return zero.
Note: A micro timer force load affects all timer channels that use the corresponding micro time base.
Module Base + 0x0001
76543210
R
00000000
W
PITFLT7
PITFLT6
PITFLT5
PITFLT4
PITFLT3
PITFLT2
PITFLT1
PITFLT0
Reset
0
00000
Figure 22-4. PIT Force Load Timer Register (PITFLT)