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Chapter 20 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
911
Read and write anytime.
CAUTION
When using the TOPNEG/BOTNEG bits and the MSKx bits at the same
time, when in complementary mode, it is possible to have both PMF channel
outputs of a channel pair set to one.
20.3.2.4
PMF Congure 3 Register (PMFCFG3)
Read and write anytime.
Table 20-4. PMFCFG2 Field Descriptions
Field
Description
5–0
MSK[5:0]
Mask PWMx
0 PWMx is unmasked.
1 PWMx is masked and the channel is set to a value of 0 percent duty cycle.
where x is 0, 1, 2, 3, 4, and 5
Address: $0003
76543210
R
PMFWAI
PMFFRZ
0
VLMODE
SWAPC
SWAPB
SWAPA
W
Reset
0
00000
= Unimplemented or Reserved
Figure 20-7. PMF Congure 3 Register (PMFCFG3)
Table 20-5. PMFCFG3 Field Descriptions
Field
Description
7
PMFWAI
PMF Stops While in WAIT Mode — When set to zero, the PWM generators will continue to run while the chip
is in WAIT mode. In this mode, the peripheral clock continues to run but the CPU clock does not. If the device
enters WAIT mode and this bit is one, then the PWM outputs will be switched to their inactive state until WAIT
mode is exited. At that point the PWM pins will resume operation as programmed in the PWM registers.
0 PMF continues to run in WAIT mode.
1 PMF is disabled in WAIT mode.
6
PMFFRZ
PMF Stops While in FREEZE Mode — When set to zero, the PWM generators will continue to run while the
chip is in FREEZE mode. If the device enters FREEZE mode and this bit is one, then the PWM outputs will be
switched to their inactive state until FREEZE mode is exited. At that point the PWM pins will resume operation
as programmed in the PWM registers.
0 PMF continues to run in FREEZE mode.
1 PMF is disabled in FREEZE mode.
4–3
VLMODE
Value Register Load Mode — This eld determines the way the value registers are being loaded. This eld can
only be written if ENHA is set.
00
Each value register is accessed independently
01
Writing to value register zero also writes to value registers one to ve
10
Writing to value register zero also writes to value registers one to three
11
Reserved (defaults to independent access)