Chapter 19 Port Integration Module (S12XFPIMV2)
MC9S12XF - Family Reference Manual, Rev.1.19
836
Freescale Semiconductor
Most I/O pins can be congured by register bits to select data direction and drive strength, to enable and
select pull-up or pull-down devices.
NOTE
The implementation of the S12XF-family Port Integration Module is device
dependent. Therefore some functions are not available on certain derivatives
or 112-pin and 80-pin package options.
19.1.2
Features
A full-featured S12XF-family Port Integration Module includes these distinctive registers:
Data and data direction registers for Ports A, B, C, D, E, K, T, S, M, P, H, J, and AD when used as
general-purpose I/O
Control registers to enable/disable pull-device and select pull-ups/pull-downs on Ports T, S, M, P,
H, and J on per-pin basis
Control registers to enable/disable pull-up devices on Port AD on per-pin basis
Single control register to enable/disable pull-ups on Ports A, B, C, D, E, and K on per-port basis
and on BKGD pin
Control registers to enable/disable reduced output drive on Ports T, S, M, P, H, J, and AD on per-
pin basis
Single control register to enable/disable reduced output drive on Ports A, B, C, D, E, and K on per-
port basis
Control registers to enable/disable open-drain (wired-or) mode on Ports S and M
Control register to congure IRQ pin operation
Free-running clock outputs
A standard port pin has the following minimum features:
Input/output selection
5V output drive with two selectable drive strengths
5V digital and analog input
Input with selectable pull-up or pull-down device
Optional features supported on dedicated pins:
Open drain for wired-or connections
Reduced input threshold to support low voltage applications
19.2
External Signal Description
This section lists and describes the signals that do connect off-chip.
Table 19-2 shows all the pins and their functions that are controlled by the S12XFPIMV2. Refer to the SoC Guide for the availability of the individual pins in the different package options.