Chapter 12 Clock Generation Module using IPLL (CGMIPLL) Block Description
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
455
12.4
Functional Description
12.4.1
Examples of IPLL divider settings
Several examples of IPLL divider settings are shown in
Table 12-6. Shaded rows indicated that these
settings are not recommended. The following rules help to achieve optimum stability and shortest lock
time:
Use lowest possible fVCO / fREF ratio (SYNDIV value).
Use highest possible REFCLK frequency fREF.
12.4.2
IPLL Operation
The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is
divided in a range of 1 to 64 (REFDIV+1) to output the REFCLK. The VCO output clock, (VCOCLK) is
fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2
x (SYNDIV +1)] to output the FBCLK. The VCOCLK can by divided by 2 (DIV2 bit) to output the
CGMIPLL Clock.
The phase detector then compares the FBCLK, with the REFCLK. Correction pulses are generated based
on the phase difference between the two signals. The loop lter then slightly alters the DC voltage on the
internal lter capacitor, based on the width and direction of the correction pulse.
The user must select the range of the REFCLK frequency and the range of the VCOCLK frequency to
ensure that the correct IPLL loop bandwidth is set.
The lock detector compares the frequencies of the FBCLK, and the REFCLK. Therefore, the speed of the
lock detector is directly proportional to the reference clock frequency. The circuit determines the lock
condition based on this comparison.
If IPLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and then check
the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously (during
IPLL start-up, usually) or at periodic intervals.
The LOCK bit is a read-only indicator of the locked state of the IPLL.
Table 12-6. Examples of IPLL Divider Settings
fOSC
REFDIV[5:0]
fREF
REFFRQ[1:0] SYNDIV[5:0]
fVCO
VCOFRQ[1:0]
DIV2
fCGMIPLL
4MHz
$00
4MHz
01
$09
80MHz
01
0
80MHz
8MHz
$00
8MHz
10
$04
80MHz
01
0
80MHz
4MHz
$00
4MHz
01
$03
32MHz
00
1
16MHz
4MHz
$01
2MHz
00
$18
100MHz
11
0
100MHz
4MHz
$03
1MHz
00
$18
50MHz
01
0
50MHz
4MHz
$03
1MHz
00
$32
100MHz
11
0
100MHz