参数资料
型号: SE97BTP,547
厂商: NXP Semiconductors
文件页数: 34/53页
文件大小: 386K
描述: IC TEMP SENSOR DIMM 8HWSON
产品培训模块: I²C Bus Fundamentals
特色产品: NXP - I2C Interface
标准包装: 1
功能: 温度监控系统(传感器),DIMM DDR 内存
传感器类型: 内部
感应温度: -40°C ~ 125°C
精确度: ±3°C(最小值)
拓扑: ADC(三角积分型),比较器,寄存器库
输出类型: I²C?/SMBus?
输出警报:
输出风扇:
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-WFDFN 裸露焊盘
供应商设备封装: 8-WSON
包装: 标准包装
产品目录页面: 847 (CN2011-ZH PDF)
其它名称: 568-5055-6
SE97B_1
?NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01  27 January 2010
34 of 53
NXP Semiconductors
SE97B
DDR memory module temp sensor with integrated SPD
[1]   When the part comes out of shutdown, the state of the EVENT
 pin will not change until after the first
temperature conversion. When the part enters shutdown, the ACT (TEMP[15]), AAW (TEMP[14]) and BAW
(TEMP[13]) bits (flip-flops) will be cleared.
[2]   The STTS424E02 allows clearing the interrupt when in comparator mode, but the other competitors do not.
 
[1]   SMBus Time-out.
0  enabled (default)
1  disabled
[2]   Shutdown time-out.
0  SMBus Time-out disabled when SHMD = 1
1  SMBus Time-out enabled when SHMD = 1 (default)
[3]   Thermal Sensor Shutdown mode.
0  active (default)
1  shutdown
1
RFU
reserved; always 0
0
DisableARA
Disable SMBus Alert Response Address (ARA).
0  SMBus ARA is enabled
1  disable SMBus ARA (default)
When either of the Critical Trip or Alarm Window lock bits is set, this bit
cannot be altered until unlocked.
Table 27.   SMBus Time-out register bit description &continued
Bit
Symbol
Description
Table 28.   SMBus register setting guide
Disable
Timeout
[1]
Enable
SDTO
[2]
SHMD
[3]
Thermal sensor
behavior
SPD behavior
Power mode
Use
0
X
0
TS is active and
SMBus TO is on
SPD read/write and
SMBus TO is on
Full power,
oscillator is running
JEDEC - SMBus for
TS and SPD
(like SE97 if TS is on)
1
X
0
TS is active and
SMBus TO is off
SPD read/write and
SMBus TO is off
Full power,
oscillator is running
I
2
C-bus - no SMBus
TO
0
1
1
TS is disabled and
SMBus TO is on
SPD read/write and
SMBus TO is on
Lower power,
oscillator is off unless
bus active or write to
SPD
JEDEC - SMBus for
TS and SPD
1
1
1
TS is disabled and
SMBus TO is off
SPD low power
read/write and
SMBus TO is off
Lower power,
oscillator is off unless
write to the SPD
I
2
C-bus - no SMBus
TO
X
0
1
TS is disabled and
SMBus TO is off
SPD low power
read-only and
SMBus TO is off
Lowest power,
oscillator is off all
the time
I
2
C-bus - no SMBus
TO (like SE97 if TS is
off)
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