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参数资料
| 型号： | SFCF2048H4BK1SA-I-QT-553-SMA |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 17/99页 |
| 文件大小： | 0K |
| 描述： | FLASH SLC UDMA/MDMA/PIO 2G |
| 视频文件： | Swissbit Manufacturing Overview |
| RoHS指令信息： | Environment Protection Declaration |
| 标准包装： | 20 |
| 系列： | C-300 |
| 存储容量： | 2GB |
| 存储器类型： | CompactFlash? |
| 其它名称： | 1052-1010 |
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Signal Name
– CSEL
(PC Card I/O Mode)
Dir.
Pin
Description
This signal is not used for this mode, but should be connected
by
the host to PC Card A25 or grounded by the host.
This internally pulled up signal is used to configure this device
as
– CSEL
(True IDE Mode)
– IOWR
(PC Card Memory Mode)
– IOWR
(PC Card I/O Mode)
a Master or a Slave when configured in the True IDE Mode.
When this pin is grounded, this device is configured as a
Master.
When the pin is open, this device is configured as a Slave.
This signal is not used in this mode.
The I/O Write strobe pulse is used to clock I/O data on the Card
Data bus into the CompactFlash Storage Card controller registers
when the CompactFlash Storage Card is configured to use the I/O
interface.
The clocking shall occur on the negative to positive edge of the
-IOWR
(True IDE Mode – Except
Ultra DMA Protocol
Active)
STOP
(True IDE Mode – Ultra
DMA Protocol Active)
– OE
(PC Card Memory Mode)
I
35
signal (trailing edge).
In True IDE Mode, while Ultra DMA mode protocol is not active,
this signal has the same function as in PC Card I/O Mode.
When Ultra DMA mode protocol is supported, this signal must be
negated before entering Ultra DMA mode protocol.
In True IDE Mode, while Ultra DMA mode protocol is active, the
assertion of this signal causes the termination of the Ultra DMA
burst.
This is an Output Enable strobe generated by the host interface.
It is used to read data from the CompactFlash Storage
in Memory Mode and to read the CIS and
– OE
(PC Card I/O Mode)
– ATASEL
(True IDE Mode)
I
9
configuration registers.
In PC Card I/O Mode, this signal is used to read the CIS and
configuration registers.
To enable True IDE Mode this input should be grounded by the
host.
In Memory Mode, this signal is set high when the CompactFlash
Storage Card is ready to accept a new data transfer
operation and is held low when the card is busy.
At power up and at Reset, the READY signal is held low (busy)
until the CompactFlash Storage Card has completed its power up
READY
(PC Card Memory Mode)
or reset function. No access of any type should be made to the
CompactFlash Storage Card during this time.
Note, however, that when a card is powered up and used with
RESET continuously disconnected or asserted, the Reset
– IREQ
(PC Card I/O Mode)
INTRQ
(True IDE Mode)
– REG
(PC Card Memory Mode)
– REG
(PC Card I/O Mode)
– DMACK
(True IDE Mode)
O
I
37
44
function of the RESET pin is disabled. Consequently, the
continuous assertion of RESET from the application of power
shall not cause the READY signal to remain continuously in the
busy state.
I/O Operation – After the CompactFlash Storage Card has been
configured for I/O operation, this signal is used as
-Interrupt Request. This line is strobed low to generate a pulse
mode interrupt or held low for a level mode interrupt.
In True IDE Mode signal is the active high Interrupt Request to
the host.
This signal is used during Memory Cycles to distinguish between
Common Memory and Register (Attribute) Memory accesses.
High for Common Memory, Low for Attribute Memory.
The signal shall also be active (low) during I/O Cycles when the
I/O address is on the Bus.
This is a DMA Acknowledge signal that is asserted by the host in
response to DMARQ to initiate DMA transfers.
While DMA operations are not active, the card shall ignore the
-DMACK signal, including a floating condition.
If DMA operation is not supported by a True IDE Mode only host,
this signal should be driven high or connected to VCC by the
host.
A host that does not support DMA mode and implements both
PCMCIA and True-IDE modes of operation need not alter the
PCMCIA mode connections while in True-IDE mode as long as
this does not prevent proper operation all modes.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.51
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-300_data_sheet_CF-HxBK_Rev151.doc
Page 17 of 99
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| SFCF2048H4BK2SA-I-DS-553-SMA | 功能描述:FLASH SLC UDMA/MDMA/PIO 2G RoHS:是 类别:存储卡，模块 >> 存储器，PC 卡 系列:C-300 标准包装:30 系列:- 存储容量:8GB 存储器类型:存储卡 - Extreme III SD? |
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