参数资料
型号: SFCF2048H4BK1SA-I-QT-553-SMA
厂商: Swissbit NA Inc
文件页数: 29/99页
文件大小: 0K
描述: FLASH SLC UDMA/MDMA/PIO 2G
视频文件: Swissbit Manufacturing Overview
RoHS指令信息: Environment Protection Declaration
标准包装: 20
系列: C-300
存储容量: 2GB
存储器类型: CompactFlash?
其它名称: 1052-1010
NOTE – If a data transfer is terminated before completion, the assertion of INTRQ should be passed through to the
host software driver regardless of whether all data requested by the command has been transferred.
6.5.2 Restrictions and Considerations During Ultra DMA Commands
There are number of important restrictions and considerations for the implementation and use of Ultra DMA
commands in CompactFlash devices. These are highlighted in the subsections below.
Additional restrictions on specific modes of operation are given in sections 5.3 and 6.5.3
6.5.2.1 System Restrictions for Ultra DMA modes 3 and above
Ultra DMA modes 3 and above are valid only for systems that meet the requirements of section 5.3
6.5.2.2 UDMA Address and Card Enable Signals
The Card Enable signals (-CE1 / -CS0 and – CE2 / -CS1) shall remain negated during Ultra DMA data bursts.
The Address bus (A[10:00]) shall not transition unnecessarily during the UDMA command and shall remain fixed
during an Ultra DMA data burst. In True IDE mode, the address lines (A[02:00]) shall be held to all zeros. This will
reduce unnecessary noise during the UDMA command.
6.5.2.3 Task File registers shall not be written during an Ultra DMA command
The task file registers shall not be written after an Ultra DMA command is issued by the host and before the
command completes. Writing to the device control register is permitted between bursts, but is expected to occur
only to reset the card after an unrecoverable protocol error.
6.5.2.4 Ultra DMA transfers shall be 16 bits wide
All transfers during an Ultra DMA data burst are 16 bit wide transfers. The Set Features command that controls the
bus width for PIO transfers does not affect the width of Ultra DMA transfers.
6.5.2.5 No Access to Memory or I/O Space during an Ultra DMA Data Burst
No access to common or attribute memory or to I/O space on the device is permitted during an Ultra DMA data
burst.
6.5.3 Specific rules for PC Card Memory Mode Ultra DMA
In addition to the general restrictions for all Ultra DMA operations, these additional considerations exist for PC
Card Memory Mode Ultra DMA operations.
6.5.3.1 No Access to Attribute Memory during PC Card Memory Mode DMA Commands
The host shall not attempt to access Attribute Memory space during a PC Card Memory Mode DMA command either
before, between or within Ultra DMA data bursts.
6.5.3.2 READY signal handling during DMA commands in PC Card Memory Mode
In PC Card Memory Mode, the READY signal shall be negated (made BUSY) by the device upon receipt of a DMA
command and shall remain negated until the command has completed at which time it shall be re-asserted.
This treatment allows the host to receive a single interrupt at the end of the command and avoids the extra
overhead that would be associated with processing busy to ready transitions for each sector transferred as is the
case when the READY toggles at the end of every sector of PIO Memory Mode transfers.
The BSY bit in the status register is permitted to be negated in the status register at any time that the DRQ bit in
the status register is asserted. The only restriction is that either DRQ or BSY or both must remain asserted while
the command is in progress.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.51
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-300_data_sheet_CF-HxBK_Rev151.doc
Page 29 of 99
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