- 您现在的位置：买卖IC网 > PDF目录7463 > SFPA4096Q1BO2TO-I-DT-223-STD (Swissbit NA Inc)FLASH SSD SMART UDMA 2.5" 4GB PDF资料下载
参数资料
| 型号： | SFPA4096Q1BO2TO-I-DT-223-STD |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 35/76页 |
| 文件大小： | 0K |
| 描述： | FLASH SSD SMART UDMA 2.5" 4GB |
| 视频文件： | Swissbit Manufacturing Overview |
| RoHS指令信息： | Environment Protection Declaration |
| 标准包装： | 4 |
| 系列： | P-120 |
| 存储容量： | 4GB |
| 存储器类型： | FLASH |
| 其它名称： | 1052-1024 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页当前第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页
7.11.3 Bit 5 (DWF)
When set this bit indicates a Write Fault has occurred.
7.11.4 Bit 4 (DSC)
This bit is set when the Drive is ready.
7.11.5 Bit 3 (DRQ)
The Data Request is set when the Drive requires information be transferred either to or from the host
through the Data register. The bit is cleared by the next command.
7.11.6 Bit 2 (CORR)
This bit is set when a Correctable data error has been encountered and the data has been corrected. This
condition does not terminate a multi-sector read operation.
7.11.7 Bit 1 (IDX)
This bit is always set to ‘0’.
7.11.8 Bit 0 (ERR)
This bit is set when the previous command has ended in some type of error. The bits in the Error register
contain additional information describing the error. In case of read or write access commands that end
with an error, the address of the first sector with an error is in the command block registers. This bit is
cleared by the next command.
Table 31: Status & Alternate Status Register
D7
BUSY
D6
RDY
D5
DWF
D4
DSC
D3
DRQ
D2
CORR
D1
0
D0
ERR
7.12 Device Control Register
The Device Control register is located at address 3F6h [376h], offset Eh.
This Write-only register is used to control the Drive interrupt request and to issue an ATA soft reset to the
Drive. This register can be written even if the device is BUSY. The bits are defined as follows:
7.12.1 Bit 7 to 3
Don’t care. The host should reset this bit to ‘0’.
7.12.2 Bit 2 (SW Rst)
This bit is set to 1 in order to force the Drive to perform an AT Disk controller Soft Reset operation. This clears
Status Register and writes Diagnostic Code in Error register after a Write or Read Sector error. The Drive
remains in Reset until this bit is reset to ‘0.’
7.12.3 Bit 1 (-Ien)
When the Interrupt Enable bit is set to ‘0’, - IREQ interrupts are enabled. When the bit is set to ‘1’, interrupts
from the Drive are disabled. This bit also controls the Int bit in the Drive Configuration and Status Register.
It is set to ‘0’ at Power On.
7.12.4 Bit 0
This bit is set to ‘0’.
Table 32: Device Control Register
D7
X(0)
D6
X(0)
D5
X(0)
D4
X(0)
D3
X(0)
D2
SW Rst
D1
-Ien
D0
0
7.13 Drive (Drive) Address Register
The Drive Address register is located at address 3F7h [377h], offset Fh.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
P-120_data_sheet_PA-QxBO_Rev100.doc
Page 35 of 76
相关PDF资料 |
PDF描述 |
|---|---|
| 3-1437667-3 | CONN BARRIER BLK DL 10CIRC .325 |
| SFSA4096Q1BR4TO-I-MS-216-STD | FLASH SSD UDMA IND 2.5" 4GB |
| 3-1437667-1 | CONN BARRIER STRIP DL 8CIRC .325 |
| SFSA4096Q1BR4TO-I-MS-226-STD | FLASH SLC UDMA/MDMA/PIO 4GB |
| SFPA2048Q1BO2TO-I-MS-223-STD | FLASH SSD SMART UDMA 2.5" 2GB |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SFPA4096Q1BO2TO-I-DT-243-STD | 制造商:SWISSBIT NA INC 功能描述:FLASH |
| SFPA-53 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Schottky Barrier Diodes |
| SFPA-63 | 制造商:SANKEN 制造商全称:Sanken electric 功能描述:Schottky Barrier Diodes (Surface Mount) 30V |
| SFPA-73 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Schottky Barrier Diodes |
| SFPA8192Q1BO2TO-C-QT-243-STD | 制造商:SWISSBIT NA INC 功能描述:FLASH |
发布紧急采购，3分钟左右您将得到回复。