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参数资料
| 型号： | SFPA4096Q1BO2TO-I-DT-223-STD |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 43/76页 |
| 文件大小： | 0K |
| 描述： | FLASH SSD SMART UDMA 2.5" 4GB |
| 视频文件： | Swissbit Manufacturing Overview |
| RoHS指令信息： | Environment Protection Declaration |
| 标准包装： | 4 |
| 系列： | P-120 |
| 存储容量： | 4GB |
| 存储器类型： | FLASH |
| 其它名称： | 1052-1024 |
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8.6.13 Word 54-56: Current Number of Cylinders, Heads, Sectors/Track
These fields contain the current number of user addressable Cylinders, Heads, and Sectors/Track in the
current translation mode.
8.6.14 Word 57-58: Current Capacity
This field contains the product of the current cylinders, heads and sectors.
8.6.15 Word 59: Multiple Sector Setting
Bits 15- 9 are reserved and must be set to ‘0’.
Bit 8 is set to ‘1’, to indicate that the Multiple Sector Setting is valid.
Bits 7-0 are the current setting for the number of sectors to be transferred for every interrupt, on
Read/Write Multiple commands; the only values returned are ‘00h’ or ‘01h’.
8.6.16 Word 60-61: Total Sectors Addressable in LBA Mode
This field contains the number of sectors addressable for the Drive in LBA mode only.
8.6.17 Word 63: Multi-Word DMA transfer
Bits 15 through 8 of word 63 of the Identify Device parameter information is defined as the Multiword DMA
mode selected field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit significant.
Only one of bits may be set to one in this field by the drive to indicate the multiword DMA mode which is
currently selected.
Of these bits, bits 15 through 11 are reserved. Bit 8, if set to one, indicates that Multiword DMA mode 0 has
been selected. Bit 9, if set to one, indicates that Multiword DMA mode 1 has been selected. Bit 10, if set to
one, indicates that Multiword DMA mode 2 has been selected.
Selection of Multiword DMA modes 3 and above are specific to Drive are as described in Word 163.
Bits 7 through 0 of word 63 of the Identify Device parameter information is defined as the Multiword DMA
data transfer supported field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit
significant. Any number of bits may be set to one in this field by the drive to indicate the Multiword DMA
modes it is capable of supporting.
Of these bits, bits 7 through 2 are reserved. Bit 0, if set to one, indicates that the drive supports Multiword
DMA mode 0. Bit 1, if set to one, indicates that the drive supports Multiword DMA modes 1 and 0. Bit 2, if set
to one, indicates that the Drive supports Multiword DMA modes 2, 1 and 0.
Support for Multiword DMA modes 3 and above are specific to Drive are reported in word 163 as described in
Word 163.
8.6.18 Word 64: Advanced PIO transfer modes supported
This field is bit significa nt. Any number of bits may be set to ‘1’ in this field by the drive to indicate the
advanced PIO modes it is capable of supporting.
1.
2.
3.
Bits 7-2 are reserved for future advanced PIO modes.
Bit 1 is set to ‘1’, indicates that the Drive supports PIO mode 4.
Bit 0 is set to ‘1’ to indicate that the Drive supports PIO mode 3.
Support for PIO modes 5 and above are specific to Drive are reported in word 163 as described in Word 163.
8.6.19 Word 65: Minimum Multi-Word DMA transfer cycle time
Word 65 of the parameter information of the Identify Device command is defined as the minimum
Multiword DMA transfer cycle time. This field defines, in nanoseconds, the minimum cycle time that, if used
by the host, the Drive guarantees data integrity during the transfer.
If this field is supported, bit 1 of word 53 shall be set to one. The value in word 65 shall not be less than the
minimum cycle time for the fastest DMA mode supported by the device. This field shall be supported by all
Drives supporting DMA modes 1 and above. If bit 1 of word 53 is set to one, but this field is not supported,
the Drive shall return a value of zero in this field.
8.6.20 Word 66: Recommended Multi-Word DMA transfer cycle time
Word 66 of the parameter information of the Identify Device command is defined as the recommended
Multiword DMA transfer cycle time. This field defines, in nanoseconds, the cycle time that, if used by the
host, may optimize the data transfer from by reducing the probability that the Drive will need to negate the
DMARQ signal during the transfer of a sector.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
P-120_data_sheet_PA-QxBO_Rev100.doc
Page 43 of 76
相关PDF资料 |
PDF描述 |
|---|---|
| 3-1437667-3 | CONN BARRIER BLK DL 10CIRC .325 |
| SFSA4096Q1BR4TO-I-MS-216-STD | FLASH SSD UDMA IND 2.5" 4GB |
| 3-1437667-1 | CONN BARRIER STRIP DL 8CIRC .325 |
| SFSA4096Q1BR4TO-I-MS-226-STD | FLASH SLC UDMA/MDMA/PIO 4GB |
| SFPA2048Q1BO2TO-I-MS-223-STD | FLASH SSD SMART UDMA 2.5" 2GB |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SFPA4096Q1BO2TO-I-DT-243-STD | 制造商:SWISSBIT NA INC 功能描述:FLASH |
| SFPA-53 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Schottky Barrier Diodes |
| SFPA-63 | 制造商:SANKEN 制造商全称:Sanken electric 功能描述:Schottky Barrier Diodes (Surface Mount) 30V |
| SFPA-73 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Schottky Barrier Diodes |
| SFPA8192Q1BO2TO-C-QT-243-STD | 制造商:SWISSBIT NA INC 功能描述:FLASH |
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