参数资料
型号: SI4704-D50-GM
厂商: Silicon Laboratories Inc
文件页数: 23/34页
文件大小: 0K
描述: IC FM RADIO RECEIVER ADV 20-QFN
标准包装: 490
频率: 64MHz ~ 108MHz
调制或协议: FM
应用: 通用
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
电源电压: 2.7 V ~ 5.5 V
工作温度: -20°C ~ 85°C
封装/外壳: 20-UFQFN 裸露焊盘
供应商设备封装: 20-QFN(3x3)
包装: 托盘
Si4704/05-D50
4.16. Control Interface
A serial port slave interface is provided, which allows an
external controller to send commands to the Si4704/05
and receive responses from the device. The serial port
can operate in two bus modes: 2-wire mode and 3-wire
mode. The Si4704/05 selects the bus mode by sampling
the state of the GPO1 and GPO2 pins on the rising
edge of RST. The GPO1 pin includes an internal pull-up
resistor, which is connected while RST is low, and the
GPO2 pin includes an internal pull-down resistor, which
is connected while RST is low. Therefore, it is only
necessary for the user to actively drive pins which differ
from these states. See Table 12.
Table 12. Bus Mode Select on Rising Edge of
RST
For write operations, the user then sends an 8-bit data
byte on SDIO, which is captured by the device on rising
edges of SCLK. The Si4704/05 acknowledges each
data byte by driving SDIO low for one cycle, on the next
falling edge of SCLK. The user may write up to 8 data
bytes in a single 2-wire transaction. The first byte is a
command, and the next seven bytes are arguments.
For read operations, after the Si4704/05 has
acknowledged the control byte, it will drive an 8-bit data
byte on SDIO, changing the state of SDIO on the falling
edge of SCLK. The user acknowledges each data byte
by driving SDIO low for one cycle, on the next falling
edge of SCLK. If a data byte is not acknowledged, the
transaction will end. The user may read up to 16 data
bytes in a single 2-wire transaction. These bytes contain
the response data from the Si4704/05.
Bus Mode
2-Wire
3-Wire
GPO1
1
0 (must drive)
GPO2
0
0
A 2-wire transaction ends with the STOP condition,
which occurs when SDIO rises while SCLK is high. For
details on timing specifications and diagrams, refer to
Table 5, “2-Wire Control Interface Characteristics” on
page 7; Figure 2, “2-Wire Control Interface Read and
After the rising edge of RST, the pins GPO1 and GPO2
are used as general purpose output (O) pins as
described in Section “4.17. GPO Outputs”. In any bus
mode, commands may only be sent after V IO and V DD
supplies are applied.
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high).
4.16.1. 2-Wire Control Interface Mode
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RST, and stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RST.
The 2-wire bus mode uses only the SCLK and SDIO
pins for signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
on SDIO, which is captured by the device on rising
edges of SCLK. The control word consists of a 7-bit
device address, followed by a read/write bit (read = 1,
write = 0). The Si4704/05 acknowledges the control
word by driving SDIO low on the next falling edge of
SCLK.
Although the Si4704/05 will respond to only a single
device address, this address can be changed with the
SEN pin (note that the SEN pin is not used for signaling
in 2-wire mode). When SEN = 0, the 7-bit device
address is 0010001b. When SEN = 1, the address is
1100011b.
Write Timing Parameters,” on page 8, and Figure 3, “2-
Wire Control Interface Read and Write Timing Diagram,”
on page 8.
4.16.2. 3-Wire Control Interface Mode
When selecting 3-wire mode, the user must ensure that
a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
The 3-wire bus mode uses the SCLK, SDIO, and SEN_
pins. A transaction begins when the user drives SEN
low. Next, the user drives a 9-bit control word on SDIO,
which is captured by the device on rising edges of
SCLK. The control word consists of a 3-bit device
address (A7:A5 = 101b), a read/write bit (read = 1, write
= 0), and a 5-bit register address (A4:A0).
For write operations, the control word is followed by a
16-bit data word, which is captured by the device on
rising edges of SCLK.
For read operations, the control word is followed by a
delay of one-half SCLK cycle for bus turn-around. Next,
the Si4704/05 will drive the 16-bit read data word
serially on SDIO, changing the state of SDIO on each
rising edge of SCLK.
A transaction ends when the user sets SEN high, then
pulses SCLK high and low one final time. SCLK may
either stop or continue to toggle while SEN is high.
In 3-wire mode, commands are sent by first writing each
argument to register(s) 0xA1–0xA3, then writing the
command word to register 0xA0. A response is
retrieved by reading registers 0xA8–0xAF.
Rev. 1.0
23
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