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参数资料
| 型号： | SI5315A-C-GMR |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 40/54页 |
| 文件大小： | 0K |
| 描述： | IC CLK MULT 8KHZ-644.53MHZ 36QFN |
| 应用说明： | SI5315/17 Crystal Selection AppNote |
| 标准包装： | 250 |
| 系列： | DSPLL® |
| 类型： | 时钟/频率倍增器，抖动衰减器，多路复用器 |
| PLL： | 无 |
| 主要目的： | 以太网，SONET/SDH/PDH，电信 |
| 输入： | CML，CMOS，LVDS，LVPECL |
| 输出： | CML，CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 644.53MHz |
| 电源电压： | 1.71 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 供应商设备封装： | 36-QFN（6x6） |
| 包装： | 带卷 (TR) |
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Si5315
Rev. 1.0
45
14
DBL2_BY
I
3-Level
Output 2 Disable/Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and
PLL bypass mode.
L = CKOUT2 enabled
M = CKOUT2 disabled
H = Bypass mode with CKOUT2 enabled. Bypass mode is
not supported with CMOS clock outputs (SFOUT = LH).
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
16
17
CKIN1+
CKIN1–
IMulti
Clock Input 1.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table of
values. The same frequency must be applied to CKIN1 and
CKIN2.
18
LOL
O
LVCMOS
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indica-
tor.
0 = PLL locked
1 = PLL unlocked
21
CS_CA
I/O
LVCMOS
Input Clock Select/Active Clock Indicator.
Input:
If manual clock selection mode is chosen
(AUTOSEL = L), this pin functions as the manual
input clock selector. This input is internally deglitched
to prevent inadvertent clock switching during
changes in the CS input state.
0 = Select CKIN1
1 = Select CKIN2
If configured as input, must be set high or low.
Output: If automatic clock selection mode is chosen
(AUTOSEL = M or H), this pin indicates which of the
two input clocks is currently the active clock. If
alarms exist on both CKIN1 and CKIN2, indicating
that the holdover state has been entered, CA will
indicate the last active clock that was used before
entering the hold state.
0 = CKIN1 active input clock
1 = CKIN2 active input clock
23
22
BWSEL1
BWSEL0
I3-Level
Loop Bandwidth Select.
Three level inputs that select the DSPLL closed loop band-
width. See Table 9 on page 20 for available settings.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Table 19. Si5315 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
相关PDF资料 |
PDF描述 |
|---|---|
| VE-2NT-MY-S | CONVERTER MOD DC/DC 6.5V 50W |
| VE-B3W-IU | CONVERTER MOD DC/DC 5.5V 200W |
| VE-B3T-IU | CONVERTER MOD DC/DC 6.5V 200W |
| VE-2NR-MY-S | CONVERTER MOD DC/DC 7.5V 50W |
| VE-B3P-IU | CONVERTER MOD DC/DC 13.8V 200W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| Si5315B-C-GM | 功能描述:时钟发生器及支持产品 Pin-Prgrmmbl SyncE Clck Mlt/Jttr Attntr RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SI5315B-C-GMR | 功能描述:时钟发生器及支持产品 Pin-Ctrl SyncE Clk Xplier/Jitt Attn 2/2 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SI5315-C | 制造商:AUK 制造商全称:AUK corp 功能描述:IRED |
| SI5315-C(B) | 制造商:AUK 制造商全称:AUK corp 功能描述:IRED |
| SI5315-C_1 | 制造商:AUK 制造商全称:AUK corp 功能描述:IRED |
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