参数资料
型号: SI5364-H-BL
厂商: Silicon Laboratories Inc
文件页数: 4/38页
文件大小: 0K
描述: IC CLK MULT SONET/SDH 99-PBGA
标准包装: 168
系列: DSPLL®
类型: 时钟发生器,扇出缓冲器(分配)
PLL:
输入: 时钟
输出: CML
电路数: 1
比率 - 输入:输出: 3:4
差分 - 输入:输出: 是/是
频率 - 最大: 675MHz
除法器/乘法器: 无/是
电源电压: 3.135 V ~ 3.465 V
工作温度: -20°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 99-LBGA
供应商设备封装: 99-BGA(11x11)
包装: 托盘
Si5364
12
Rev. 2.5
Clock Output Phase Step Slope3—Manual
Switches
BWSEL[1:0] = 11
BWSEL[1:0] = 00
BWSEL[1:0] = 01
BWSEL[1:0] = 10
mPT
During Clock Switching
6400 Hz
3,200 Hz
1600 Hz
800 Hz
10
5
2.5
1.25
ps/
μs
Clock Output Phase Step Slope3—Auto
Switching
BWSEL[1:0] = 11
BWSEL[1:0] = 00
BWSEL[1:0] = 01
BWSEL[1:0] = 10
mPT
During Clock Switching
6400 Hz
3200 Hz
1600 Hz
800 Hz
36
18
9.0
4.5
ps/
μs
Transient Phase Deviation During Clock
Auto Switching
BWSEL[1:0] = 11
BWSEL[1:0] = 00
BWSEL[1:0] = 01
BWSEL[1:0] = 10
tpt_mtie_max
6400 Hz
3200 Hz
1600 Hz
800 Hz
800
ps
Table 5. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
3.3 V DC Supply Voltage
VDD33
–0.5 to 3.6
V
LVTTL Input Voltage
VDIG
–0.3 to (+3.6)
V
Maximum Current Any Output PIN
±50
mA
Operating Junction Temperature
TJCT
–55 to 150
°C
Storage Temperature Range
TSTG
–55 to 150
°C
ESD HBM Tolerance (100 pf, 1.5 k
Ω)1.0
kV
Note:
Permanent device damage can occur if the Absolute Maximum Ratings are exceeded. Restrict functional operation to
the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods might affect device reliability.
Table 6. Thermal Characteristics
Parameter
Symbol
Test Condition
Value
Unit
Thermal Resistance Junction to Ambient
θJA
Still Air
34.9
°C/W
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD33 = 3.3 V ± 5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Notes:
1.
Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2.
For reliable device operation, temperature gradients should be limited to 10 °C/min.
3.
Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
of nanoseconds per millisecond. The equivalent ps/
μs unit is used here since the maximum phase transient magnitude
for the Si5364 (tPT_MTIE) never reaches one nanosecond.
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