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| 型号： | SI5364-H-BL |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 8/38页 |
| 文件大小： | 0K |
| 描述： | IC CLK MULT SONET/SDH 99-PBGA |
| 标准包装： | 168 |
| 系列： | DSPLL® |
| 类型： | 时钟发生器，扇出缓冲器（分配） |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CML |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:4 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 675MHz |
| 除法器/乘法器： | 无/是 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 99-LBGA |
| 供应商设备封装： | 99-BGA（11x11） |
| 包装： | 托盘 |
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Si5364
16
Rev. 2.5
2.1.1. FEC Rate Conversion
Conversion from non-FEC to FEC rates and from FEC
to non-FEC rates is supported with selectable 238/255
or 255/238 scaling of the Si5364’s clock output
multiplication ratios.
The multiplication ratios and associated frequency
ranges for the Si5364 clock outputs are set by the
FRQSEL[1:0] pins associated with each clock output.
Additional frequency scaling of active clock outputs by a
factor of either 238/255 or 255/238 is selected using the
FEC[1:0] control inputs.
For example, a 622.08 MHz output clock (a non-FEC
rate) is generated from a 19.44 MHz input clock (a non-
FEC
rate)
by
setting
FRQSEL[1:0] = 11
(32x
multiplication) and setting FEC[1:0] = 00 (no FEC
scaling). A 666.51 MHz output clock (a FEC rate) is
generated from a 19.44 MHz input clock (a non-FEC
rate) by setting FRQSEL[1:0] = 11 (32x multiplication)
and setting FEC[1:0] = 01 (255/238 FEC scaling).
Finally, a 622.08 MHz output clock (a non-FEC rate) is
generated from a 20.83 MHz input clock (a FEC rate) by
setting FRQSEL [1:0] = 11 (32x multiplication) and
setting FEC[1:0] = 10 (238/255 FEC scaling). The
FEC[1:0] settings and associated scaling factors are
listed in Table 9.
2.2. PLL Performance
The Si5364 PLL provides extremely low jitter
generation, high jitter tolerance, and a well-controlled
jitter transfer function with low peaking and a high
degree of jitter attenuation. Each of these key
performance parameters is described in the following
sections.
2.2.1. Jitter Tolerance
Jitter tolerance for the Si5364 is defined as the
maximum peak-to-peak sinusoidal jitter that can be
present on the incoming clock. Tolerance is a function of
the input jitter frequency and improves for lower input
jitter frequency.
Figure 8. Jitter Tolerance Mask/Template
Figure 9. PLL Jitter Transfer Mask/Template
2.2.2. Jitter Transfer
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter for a specified jitter frequency. The
jitter transfer characteristic determines the amount of
input clock jitter that passes to the outputs. The DSPLL
technology used in the Si5364 provides tightly
controlled jitter transfer curves because the PLL gain
parameters are determined by digital circuits that do not
vary over supply voltage, process, and temperature. In
a system application, a well-controlled transfer curve
minimizes the output clock jitter variation from board to
board for consistent system-level jitter performance.
The jitter transfer characteristic is a function of the
BWSEL[1:0] setting. Lower bandwidth selection results
in more jitter attenuation of the incoming clock but might
result in higher jitter generation. Table 4 on page 9 gives
the 3 dB bandwidth and peaking values for specified
BWSEL[1:0] settings. Figure 9 shows the jitter transfer
curve mask.
2.2.3. Jitter Generation
Jitter generation is defined as the amount of jitter
produced at the output of the device with a jitter-free
input clock. Jitter is generated from sources within the
VCO and other PLL components. Jitter generation is a
function of the PLL bandwidth setting.
Table 9. FEC Rate Conversion
FEC Frequency
Scaling
FEC1
FEC0
FSYNC
1/1
0
Enabled
255/238
0
1
Disabled
238/255
1
0
Enabled
Reserved
1
Input
Jitter
Amplitude
10 ns
F
BW
–20 dB/dec.
f
Jitter In
Excessive Input Jitter Range
Jitter
Transfer
0 dB
F
BW
f
Jitter
Peaking
–20 dB/dec.
Jitter Out
Jitter In
(s)
相关PDF资料 |
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| SI5365-C-GQ | IC CLOCK MULTIPLIER PROG 100TQFP |
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| SI5367A-C-GQ | IC CLOCK MULTIPLIER PROG 100TQFP |
| SI5368A-C-GQ | IC CLK MULTIPLIER ATTEN 100TQFP |
| SI5369A-C-GQ | IC CLK MULT JITTER ATTEN 100TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| Si5364-H-BLR | 功能描述:时钟发生器及支持产品 SONET/SDH Precision 19MHz 155MHz 622MHz RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5364-H-GL | 功能描述:时钟发生器及支持产品 SONET/SDH Prcsn Port Card Clock Multiplr RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5364-H-GLR | 功能描述:时钟发生器及支持产品 SONET/SDH Precision 19MHz 155MHz 622MHz RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SI5365 | 制造商:SILABS 制造商全称:SILABS 功能描述:PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER |
| Si5365/66-EVB | 功能描述:时钟和定时器开发工具 Si5365/Si5366 EVAL BOARD RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V |
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