参数资料
型号: SI5484DU-T1-GE3
厂商: Vishay Siliconix
文件页数: 1/9页
文件大小: 0K
描述: MOSFET N-CH 20V 12A PPAK CHIPFET
标准包装: 3,000
系列: TrenchFET®
FET 型: MOSFET N 通道,金属氧化物
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 20V
电流 - 连续漏极(Id) @ 25° C: 12A
开态Rds(最大)@ Id, Vgs @ 25° C: 16 毫欧 @ 7.6A,4.5V
Id 时的 Vgs(th)(最大): 2V @ 250µA
闸电荷(Qg) @ Vgs: 55nC @ 10V
输入电容 (Ciss) @ Vds: 1600pF @ 10V
功率 - 最大: 31W
安装类型: 表面贴装
封装/外壳: PowerPAK? CHIPFET? 单
供应商设备封装: PowerPAK? ChipFET 单通道
包装: 带卷 (TR)
Si5484DU
Vishay Siliconix
N-Channel 20-V (D-S) MOSFET
PRODUCT SUMMARY
V DS (V) R DS(on) ( Ω )
I D (A) a
Q g (Typ.)
FEATURES
? Halogen-free
? TrenchFET ? Power MOSFET
20
0.016 at V GS = 4.5 V
0.021 at V GS = 2.5 V
12
12
16.5 nC
? New Thermally Enhanced PowerPAK ?
ChipFET ? Package
- Small Footprint Area
RoHS
COMPLIANT
- Low On-Resistance
- Thin 0.8 mm Profile
PowerPAK ChipFET Sin g le
1
2
D
3
APPLICATIONS
? Load Switch, PA Switch, and for Portable Applications
D
8
D
7
D
6
D
D
S
D
S
G
4
Marking Code
AF XXX
Lot Tracea b ility
and Date Code
G
5
Bottom V ie w
Orderin g Information: Si54 8 4DU-T1-GE3 (Lead (P b )-free and Halogen-free)
Part # Code
S
N -Channel MOSFET
ABSOLUTE MAXIMUM RATINGS T A = 25 °C, unless otherwise noted
Parameter
Drain-Source Voltage
Gate-Source Voltage
T C = 25 °C
Symbol
V DS
V GS
Limit
20
± 12
12 a
Unit
V
Continuous Drain Current (T J = 150 °C)
Pulsed Drain Current
Continuous Source-Drain Diode Current
T C = 70 °C
T A = 25 °C
T A = 70 °C
T C = 25 °C
T A = 25 °C
T C = 25 °C
I D
I DM
I S
12 a
11.4 b, c
9.1 b, c
40
12 a
2.6 b, c
31
A
Maximum Power Dissipation
T C = 70 °C
T A = 25 °C
P D
20
3.1 b, c
W
T A = 70 °C
2 b, c
Soldering Recommendations (Peak Temperature)
Operating Junction and Storage Temperature Range
d, e
T J , T stg
- 55 to 150
260
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
Maximum Junction-to-Ambient b, f
Maximum Junction-to-Case (Drain)
t ≤ 5s
Steady State
R thJA
R thJC
34
3
40
4
°C/W
Notes:
a. Package limited.
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. See Solder Profile ( http://www.vishay.com/ doc ?73257 ). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under Steady State conditions is 90 °C/W.
Document Number: 73589
S-81448-Rev. B, 23-Jun-08
www.vishay.com
1
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