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| 型号： | SI7110DN-T1-GE3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 20V 13.5A 1212-8 |
| 产品目录绘图： | DN-T1-E3 Series 1212-8 |
| 标准包装： | 1 |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 20V |
| 电流 - 连续漏极(Id) @ 25° C： | 13.5A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 5.3 毫欧 @ 21.1A，10V |
| Id 时的 Vgs(th)（最大）： | 2.5V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 21nC @ 4.5V |
| 功率 - 最大： | 1.5W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | PowerPAK? 1212-8 |
| 供应商设备封装： | PowerPAK? 1212-8 |
| 包装： | 标准包装 |
| 产品目录页面： | 1660 (CN2011-ZH PDF) |
| 其它名称： | SI7110DN-T1-GE3DKR |
AN822
Vishay Siliconix
PowerPAK 1212 DUAL
To take the advantage of the dual PowerPAK 1212-8’s
thermal performance, the minimum recommended
land pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs . Click
on the PowerPAK 1212-8 dual in the index of this doc-
ument.
The gap between the two drain pads is 10 mils. This
matches the spacing of the two drain pads on the Pow-
erPAK 1212-8 dual package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
ture profile used, and the temperatures and time
duration, are shown in Figures 2 and 3. For the lead
(Pb)-free solder profile, see http://www.vishay.com/
doc?73257.
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in 2 of will yield little improve-
ment in thermal performance.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder
Ramp-Up Rate
Temperature at 155 ± 15 ° C
Temperature Above 180 ° C
Maximum Temperature
Time at Maximum Temperature
Ramp-Down Rate
+ 6 ° C /Second Maximum
120 Seconds Maximum
70 - 180 Seconds
240 + 5/- 0 ° C
20 - 40 Seconds
+ 6 ° C/Second Maximum
reflow reliability requirements. Devices are subjected
to solder reflow as a preconditioning test and are then
Figure 2. Solder Reflow Temperature Profile
reliability-tested using temperature cycle, bias humid-
ity, HAST, or pressure pot. The solder reflow tempera-
10 s (max)
210 - 220 °C
140 - 170 °C
3 ° C/s (max)
1 8 3 °C
50 s (max)
4 ° C/s (max)
3° C/s (max)
60 s (min)
Reflo w Zone
Pre-Heating Zone
Maxim u m peak temperat u re at 240 °C is allo w ed.
Figure 3. Solder Reflow Temperatures and Time Durations
www.vishay.com
2
Document Number 71681
03-Mar-06
相关PDF资料 |
PDF描述 |
|---|---|
| SI7115DN-T1-E3 | MOSFET P-CH D-S 150V PPAK 1212-8 |
| SI7120DN-T1-GE3 | MOSFET N-CH 60V 6.3A 1212-8 |
| SI7123DN-T1-GE3 | MOSFET P-CH 20V 10.2A 1212-8 |
| SI7129DN-T1-GE3 | MOSFET P-CH D-S 30V 1212-8 |
| SI7135DP-T1-GE3 | MOSFET P-CH 30V 60A PPAK 8SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SI7112DN-T1-E3 | 功能描述:MOSFET 30V 17.8A 3.8W 7.5mohm @ 10V RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| SI7112DN-T1-GE3 | 功能描述:MOSFET 30V 17.8A 3.8W 7.5mohm @ 10V RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| SI7113DN | 制造商:VISHAY 制造商全称:Vishay Siliconix 功能描述:P-Channel 100-V (D-S) MOSFET |
| SI7113DN-T1-E3 | 功能描述:MOSFET 100V 13.2A 52W RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| SI7113DN-T1-GE3 | 功能描述:MOSFET 100V 13.2A 52W 134mohm @ 10V RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
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