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参数资料
| 型号： | SMFR-29C516ESC |
| 厂商： | TEMIC SEMICONDUCTORS |
| 元件分类： | 算术逻辑单元 |
| 英文描述： | 16-BIT ERROR DETECT AND CORRECT CKT, QFP100 |
| 封装： | MQFP-100 |
| 文件页数： | 11/42页 |
| 文件大小： | 809K |
| 代理商： | SMFR-29C516ESC |
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Signal name
Pin
Type
Active state
Description
TN
96
I
High/Low
Transfer : Select the data path to be used.
If this signal is high the EDAC accesses
the memory, ant if it is low it accesses the
Transfer buffer
U2/U1N
95
I
High/Low
Selects who is the master of User1 and
User 2. The Master is responsible for
applying R/WxN, MxN and ENxN signals
in a correct way.
CORRECT
98
I
High
Selects CORRECTION mode. If Low, the
EDAC is in DETECT mode.
SYCHN
97
I
Low
Selects the SYndrome bits (high byte) and
the CHeck bits (low byte) to be driven on
the selected user data bus.
N22
27
I
High
When active the EDAC uses six check
bits, when inactive the EDAC uses eight
check bits in memory read.
CERRN
26
O, BUF
Low
Correctable error flag.
NCERRN
25
O, BUF
Low
Uncorrectable error flag.
VCCB (VDD)
9, 19, 32,
41, 54, 63,
73, 87
PS
Buffer supply (5V nominal)
GNDB (VSS)
4, 14, 24,
36, 46, 58,
68, 78, 92
PS
Buffers 0V reference
VCCC (VDD)
100
PS
Core supply (5V nominal)
GNDC
93
PS
Core 0V reference
The EDAC has 69 signal pins, whereof 11 are inputs, 2 are outputs and 56 are I/Os.
Document number
MHS/SCC 021
Date
Issue
Page
23/12/1999
Rev C
19
Rev C
19 /42
TEMI C
Semiconductors
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