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参数资料
| 型号： | SMQ320C32PCMM50 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 24-BIT, 50 MHz, OTHER DSP, PQFP144 |
| 封装： | PLASTIC, QFP-144 |
| 文件页数： | 31/50页 |
| 文件大小： | 674K |
| 代理商： | SMQ320C32PCMM50 |
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 19998
37
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing for HOLD/ HOLDA [P = tc(H)] (see Note 8 and Figure 31)
NO
’320C32-50
’320C32-60
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
80
tsu(HOLD)
Setup time, HOLD before H1 low
10
8
ns
81
tv(HOLDA)
Valid time, HOLDA after H1 low
0*
7
0*
6
ns
82
tw(HOLD)
Pulse duration, HOLD low
2P
ns
83
tw(HOLDA)
Pulse duration, HOLDA low
P–5*
ns
84
td(H1L-SH)H
Delay time, H1 low to STRBx high for a HOLD
0*
7*
0*
6*
ns
84.1
td(H1H-IOS)H Delay time, H1 high to IOSTRB high for a HOLD
0*
7*
0*
6*
ns
85
tdis(H1L-S)
Disable time, H1 low to STRBx or IOSTRB (in the high-impedance
state)
0*
8*
0*
7*
ns
86
ten(H1L-S)
Enable time, H1 low to STRBx or IOSTRB active
0*
7*
0*
6*
ns
87
tdis(H1L-RW)
Disable time, H1 low to R/W in the high-impedance state
0*
8*
0*
7*
ns
88
ten(H1L-RW)
Enable time, H1 low to R/W (active)
0*
7*
0*
6*
ns
89
tdis(H1L-A)
Disable time, H1 low to A in the high-impedance state
0*
8*
0*
7*
ns
90
ten(H1L-A)
Enable time, H1 low to A valid
0*
12*
0*
11*
ns
91
tdis(H1H-D)
Disable time, H1 high to D disabled in the high-impedance state
0*
8*
0*
7*
ns
* This parameter is not production tested.
NOTE 8: HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact
sequence shown occurs; otherwise, an additional delay of one clock cycle can occur. The NOHOLD bit of the primary-bit-control register
overwrites the HOLD signal.
IOSTRB
STRBx
H3
H1
HOLD
HOLDA
(see Note A)
R/W
A
D
80
81
82
81
83
85
87
86
88
90
89
91
84
Write Data
85
86
84.1
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle after HOLD goes back high.
Figure 31. HOLD / HOLDA Timing
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