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参数资料
| 型号： | SMQ320C32PCMM50 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 24-BIT, 50 MHz, OTHER DSP, PQFP144 |
| 封装： | PLASTIC, QFP-144 |
| 文件页数： | 49/50页 |
| 文件大小： | 674K |
| 代理商： | SMQ320C32PCMM50 |
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
external memory interface (continued)
Up to three mutually exclusive memory areas—one program area and two data areas—can be implemented.
Each memory area configuration is independent of the physical memory width and independent of the other
memory areas configurations. See Figure 1.
’C32
Strobe-
Control
Registers
32-Bit
CPU
PRGW Pin
STRB0
STRB1
IOSTRB
Memory
Interface
8-/16-/32-Bit Data in
8-/16-/32-Bit-Wide Memory
32-Bit Program in 16-/32-Bit-
Wide Memory
8-/16-/32-Bit Data in
8-/16-/32-Bit-Wide Memory
32-Bit Data in 32-Bit-Wide
Memory
32-Bit Program in 16-/32-Bit-
Wide Memory
32-Bit Program in 32-Bit-
Wide Memory
Figure 1. ’C32 External Memory Interface
The SMQ320C32 external memory configuration is controlled by a combination of hardware configuration and
memory-mapped control registers and can be reconfigured dynamically. The signals that control external
memory configuration are the PRGW, STRB0, STRB1, and IOSTRB. The signals work as follows:
D The SMQ320C32 is a 32-bit microprocessor, that is, the CPU operates on 32-bit program words. The
external memory interface provides the capability of fetching instructions as either 32-bit words or two 16-bit
half words from consecutive addresses. Program memory width is 16 bits if the PRGW signal is high,
32 bits if the PRGW signal is low.
D STRB0 and STRB1 are sets of control signals, four signals each, that are mapped to specific ranges of
external memory addresses. When an address within one of these ranges is accessed by a read or write
instruction (CPU or DMA), the corresponding set of control signals is activated. Figure 8 illustrates the
SMQ320C32 memory map, showing the address ranges for which the strobe signals become active.
The behavior of the STRB0 and STRB1 control signals is determined by the contents of the STRB0 and STRB1
control registers.
The STRB0 and STRB1 control registers each have a field that specifies the physical memory width (8, 16, or
32 bits) of the external memory address ranges they control. Another field specifies the data width (8, 16, or
32 bits) of the data contained in those addresses. The values in these fields are not required to match. For
example, a 32-bit-wide physical memory space can be configured to segment each 32-bit word into four
consecutive 8-bit locations, each having its own address.
Each control signal set has two pins (STRBx_B2/A–2 and STRBx_B3/A–1) that can act as either byte-enable
(chip-select) pins or address pins, and two dedicated byte-enable (chip-select) pins (STRBx_B0 and
STRBx_B1). The pins’ functions are determined by the physical memory width specified in the corresponding
control register:
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相关代理商/技术参数 |
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| SMQ320C50 | 制造商:TI 制造商全称:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSOR |
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