![](http://datasheet.mmic.net.cn/140000/SMQ320C32PCMM60_datasheet_5012305/SMQ320C32PCMM60_45.png)
Military Operating Temperature Range
- 55°C to 125°C; QML Processing
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High-Performance Floating-Point Digital Signal Processor (DSP)
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SMQ320C32-50 (5 V)
40-ns Instruction Cycle Time
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275 MOPS
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50 MFLOPS
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25 MIPS
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SMQ320C32-60 (5 V)
33-ns Instruction Cycle Time
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330 MOPS
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60 MFLOPS
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30 MIPS
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32-Bit High-Performance CPU
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16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations
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32-Bit Instruction Word, 24-Bit Addresses
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Two 256 × 32-Bit Single-Cycle, Dual-Access On-Chip RAM Blocks
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Flexible Boot-Program Loader
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On-Chip Memory-Mapped Peripherals:
One Serial Port
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Two 32-Bit Timers
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Two-Channel Direct Memory Access (DMA) Coprocessor With Configurable Priorities
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Enhanced External Memory Interface That Supports 8-/16-/32-Bit-Wide External RAM for Data
Access and Program Execution From 16-/32-Bit-Wide External RAM
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SMJ320C30 and SMJ320C31 Object Code Compatible
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Fabricated Using 0.7-um Enhanced Performance Implanted CMOS (EPICTM) Technology by
Texas Instruments
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144-Pin Plastic Quad Flatpack
(PCM Suffix) 5 V
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Eight Extended-Precision Registers
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Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic
Units (ARAUs)
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Two Low-Power Modes
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Two- and Three-Operand Instructions
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Parallel Arithmetic Logic Unit (ALU) and Multiplier Execution in a Single Cycle
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Block-Repeat Capability
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Zero-Overhead Loops With Single-Cycle Branches
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Conditional Calls and Returns
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Interlocked Instructions for Multiprocessing Support
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One External Pin, PRGW, That Configures the External-Program-Memory Width to
16 or 32 Bits
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Two Sets of Memory Strobes ( STRB0\ and STRB1\) and One I/O Strobe ( IOSTRB\) Allow
Zero-Glue Logic Interface to Two Banks of Memory and One Bank of External Peripherals
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Separate Bus-Control Registers for Each Strobe-Control Wait-State Generation, External Memory
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Product Folder:SMQ320C32 - Digital Signal Processor
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