参数资料
型号: SN54LVTH182514
厂商: Texas Instruments, Inc.
英文描述: 3.3-V ABT Scan Test Device With 20-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(20位通用总线收发器))
中文描述: 的3.3V ABT生根粉扫描测试设备与20位通用总线收发器(3.3VABT扫描测试装置(20位通用总线收发器))
文件页数: 17/34页
文件大小: 734K
代理商: SN54LVTH182514
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS670A – AUGUST 1996 – REVISED JUNE 1997
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
parallel-signature analysis (PSA)
Data appearing at the selected device input-mode I/O pins is compressed into a 40-bit parallel signature in the
shift-register elements of the selected BSCs on each rising edge of TCK. Data in the shadow latches of the
selected output-mode BSCs remains constant and is applied to the associated device I/O pins. Figures 7 and 8
illustrate the 40-bit linear-feedback shift-register algorithms through which the signature is generated. An initial
seed value should be scanned into the BSR before performing this operation.
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
B10-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
A8-I/O
A10-I/O
A17-I/O
A16-I/O
A15-I/O
A14-I/O
A13-I/O
A12-I/O
A11-I/O
A18-I/O
A20-I/O
B18-I/O
B17-I/O
B16-I/O
B15-I/O
B14-I/O
B13-I/O
B12-I/O
B11-I/O
B20-I/O
B9-I/O
A9-I/O
A19-I/O
B19-I/O
=
=
Figure 7. 40-Bit PSA Configuration (OEAB = 0, OEBA = 1)
P
相关PDF资料
PDF描述
SN74LVTH182514 3.3-V ABT Scan Test Device With 20-Bit Universal Bus Transceivers(3.3V ABT扫描测试装置(20位通用总线收发器))
SN54LVTH18516 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(18位通用总线收发器))
SN74LVTH18516 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(18位通用总线收发器))
SN54LVTH182516 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(18位通用总线收发器))
SN74LVTH182516 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3V ABT扫描测试装置(18位通用总线收发器))
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