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| 型号： | SN54LVTH182514 |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V ABT Scan Test Device With 20-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(20位通用总线收发器)) |
| 中文描述： | 的3.3V ABT生根粉扫描测试设备与20位通用总线收发器（3.3VABT扫描测试装置（20位通用总线收发器）） |
| 文件页数： | 2/34页 |
| 文件大小： | 734K |
| 代理商： | SN54LVTH182514 |
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SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS670A – AUGUST 1996 – REVISED JUNE 1997
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type
flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the
TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the
boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the
SCOPE
universal bus transceivers.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
clock-enable (CLKENAB and CLKENBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while
CLKENAB is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and
CLKENAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs
are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to
A-to-B data flow, but uses the OEBA, LEBA, CLKENBA, and CLKBA inputs.
In the test mode, the normal operation of the SCOPE
universal bus transceivers is inhibited, and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs
other testing functions, such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern
generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The B-port outputs of ’LVTH182514, which are designed to source or sink up to 12 mA, include equivalent 25-
series resistors to reduce overshoot and undershoot.
The SN54LVTH18514 and SN54LVTH182514 are characterized for operation over the full military temperature
range of –55
°
C to 125
°
C. The SN74LVTH18514 and SN74LVTH182514 are characterized for operation from
–40
°
C to 85
°
C.
FUNCTION TABLE
(normal mode, each register)
INPUTS
OUTPUT
B
B0
L
OEAB
L
LEAB
L
CLKENAB
L
CLKAB
L
↑
↑
X
A
X
L
L
L
L
L
L
L
H
H
L
L
H
X
B0
L
L
H
X
X
L
L
H
X
X
H
H
H
X
X
X
X
Z
A-to-B data flow is shown. B-to-A data flow is similar, but uses
OEBA, LEBA, CLKENBA, and CLKBA.
Output level before the indicated steady-state input conditions were
established
P
相关PDF资料 |
PDF描述 |
|---|---|
| SN74LVTH182514 | 3.3-V ABT Scan Test Device With 20-Bit Universal Bus Transceivers(3.3V ABT扫描测试装置(20位通用总线收发器)) |
| SN54LVTH18516 | 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(18位通用总线收发器)) |
| SN74LVTH18516 | 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(18位通用总线收发器)) |
| SN54LVTH182516 | 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(18位通用总线收发器)) |
| SN74LVTH182516 | 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3V ABT扫描测试装置(18位通用总线收发器)) |
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