参数资料
型号: SN74GTLPH16912DL
厂商: TEXAS INSTRUMENTS INC
元件分类: 总线收发器
英文描述: GTL/TVC SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
封装: SSOP-56
文件页数: 1/10页
文件大小: 143K
代理商: SN74GTLPH16912DL
SN74GTLPH16912
18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVER
SCES288 – OCTOBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, and Clock-Enabled Mode
D Bidirectional Interface Between GTL+
Signal Levels and LVTTL Logic Levels
D LVTTL Interfaces Are 5-V Tolerant
D Identical to ’16601 Function
D Medium-Drive GTL+ Outputs (50 mA)
D LVTTL Outputs (–24 mA/24 mA)
D GTL+ Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity
D Ioff, Power-Up 3-State, and BIAS VCC
Support Live Insertion
D Bus Hold on A-Port Data Inputs
D Distributed VCC and GND-Pin Configuration
Minimizes High-Speed Switching Noise
D Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and Shrink
Small-Outline (DL) Packages
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR, and
the DGVR package is abbreviated to VR.
description
The SN74GTLPH16912 is a medium-drive 18-bit
universal bus transceiver (UBT) that provides
LVTTL-to-GTL+ and GTL+-to-LVTTL signal-level
translation. It allows for transparent, latched,
clocked, and clock-enabled modes of data transfer identical to the ’16601 function. The device provides a
high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTL+ signal
levels. High-speed (about two times faster than standard TTL or LVTTL) backplane operation is a direct result
of GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, and output
edge control (OEC
). Improved GTLP OEC circuits minimize bus settling time and have been designed and
tested using several backplane models. The medium drive is suitable for driving double-terminated backplanes.
GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3.
The AC specification of the SN74GTLPH16912 is given only at the preferred higher noise margin GTL+, but
the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTL+ (VTT = 1.5
V and VREF = 1 V) signal levels.
Normally, the B port operates at GTL or GTL+ levels, while the A-port and control inputs are compatible with
LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port.
PRODUCT
PREVIEW
Copyright
1999, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC and UBT are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
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56
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OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
CEAB
CLKAB
B1
GND
B2
B3
BIAS VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VREF
B16
B17
GND
B18
CLKBA
CEBA
相关PDF资料
PDF描述
SN74GTLPH16945DGGR GTLP SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48
SN74GTLPH306PWLE GTL/TVC SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24
SN74H102N TTL/H/L SERIES, NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
SN74H102J TTL/H/L SERIES, NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14
SN74H106N TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
相关代理商/技术参数
参数描述
SN74GTLPH16912GR 功能描述:转换 - 电压电平 18-Bit LVTTL-to-GTLP Univ Bus Transceiver RoHS:否 制造商:Micrel 类型:CML/LVDS/LVPECL to LVCMOS/LVTTL 传播延迟时间:1.9 ns 电源电流:14 mA 电源电压-最大:3.6 V 电源电压-最小:3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MLF-8
SN74GTLPH16912VR 功能描述:总线收发器 18-Bit LVTTL-to-GTLP Univ Bus Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel
SN74GTLPH16916GR 功能描述:特定功能逻辑 17-Bit LVTTL-to-GTLP Univ Bus Trnscvr RoHS:否 制造商:Texas Instruments 产品: 系列:SN74ABTH18502A 工作电源电压:5 V 封装 / 箱体:LQFP-64 封装:Tube
SN74GTLPH16916VR 功能描述:特定功能逻辑 17-Bit LVTTL-to-GTLP Univ Bus Trnscvr RoHS:否 制造商:Texas Instruments 产品: 系列:SN74ABTH18502A 工作电源电压:5 V 封装 / 箱体:LQFP-64 封装:Tube
SN74GTLPH16927GR 功能描述:特定功能逻辑 18-Bit LVTTL-to-GTLP Bus Trnscvr RoHS:否 制造商:Texas Instruments 产品: 系列:SN74ABTH18502A 工作电源电压:5 V 封装 / 箱体:LQFP-64 封装:Tube