参数资料
型号: SN74GTLPH16912DL
厂商: TEXAS INSTRUMENTS INC
元件分类: 总线收发器
英文描述: GTL/TVC SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
封装: SSOP-56
文件页数: 3/10页
文件大小: 143K
代理商: SN74GTLPH16912DL
SN74GTLPH16912
18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVER
SCES288 – OCTOBER 1999
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
The SN74GTLPH16912 is characterized for operation from –40
°C to 85°C.
functional description
The SN74GTLPH16912 is a medium-drive (50 mA) 18-bit UBT containing D-type latches and D-type flip-flops
for data-path operation in transparent, latched, clocked, or clock-enabled modes and can replace any of the
functions shown in Table 1.
Table 1. SN74GTLPH16912 UBT Replacement Functions
FUNCTION
8 BIT
9 BIT
10 BIT
16 BIT
18 BIT
Transceiver
’245, ’623, ’645
’863
’861
’16245, ’16623
’16863
Buffer/driver
’241, ’244, ’541
’827
’16241, ’16244, ’16541
’16825
Latched transceiver
’543
’16543
’16472
Latch
’373, ’573
’843
’841
’16373
’16843
Registered transceiver
’646, ’652
’16646, ’16652
’16474
Flip-flop
’374, ’574
’821
’16374
Standard UBT
’16500, ’16501
Universal bus driver
’16835
Registered transceiver with CLK enable
’2952
’16470, ’16952
Flip-flop with CLK enable
’377
’823
’16823
Standard UBT with CLK enable
’16600, ’16601
SN74GTLPH16912 UBT replaces all above functions
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by clock-enable (CEAB and CEBA) inputs.
OEAB and OEBA control the 18 bits of data for the A-to-B and B-to-A directions, respectively.
For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the
A data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored
in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is low, the outputs
are active. When OEAB is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that for A to B, but uses OEBA, LEBA, CLKBA, and CEBA.
PRODUCT
PREVIEW
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