参数资料
型号: SP691ACT-L
厂商: Exar Corporation
文件页数: 13/24页
文件大小: 0K
描述: IC SUPERVISOR MPU LP 16WSOIC
标准包装: 41
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极,推挽式
复位: 高有效/低有效
复位超时: 最小为 140 ms
电压 - 阀值: 4.65V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 管件
其它名称: SP691ACT-L-ND
W a t c h d o g T i m e o u t P e r i o d
O S C S E L
O S C I N
N o r m a l
I m m e d i a t e l y A f t e r R e s e t
R e s e t T i m e o u t P e r i o d
L O W
L O W
F l o a t i n g
F l o a t i n g
E x t e r n a l C l o c k I n p u t
E x t e r n a l C a p a c i t o r
L O W
F l o a t i n g
1 0 2 4 c l o c k s
( 6 0 0 / 4 7 p F x C ) m s
1 0 0 m s
1 . 6 s
4 0 9 6 c l o c k s
( 2 . 4 / 4 7 p f x C ) s e c
1 . 6 s
1 . 6 s
2 0 4 8 c l o c k s
( 1 2 0 0 / 4 7 p F x C ) m s
2 0 0 m s
2 0 0 m s
Table 1. Reset Pulse Width and Watchdog Timeout Selections
RESET and RESET are asserted for the reset
timeout period (200ms nominal). WDO goes
to logic low and remains low until the next
transition at WDI. Refer to Figure 20 . If WDI
is held high or low indefinitely, RESET and
RESET will generate 200ms pulses every 1.6s.
WDO has a 2 x TTL output characteristic.
Selecting an Alternative Watchdog
Timeout Period
The OSC SEL and OSC IN inputs control the
watchdog are reset timeout periods. Floating
OSC SEL and OSC IN or tying them both to V OUT
selects the nominal 1.6s watchdog timeout
period and 200ms reset timout period.
Connecting OSC IN to ground and floating or
connecting OSC SEL to V OUT selects a 100ms nor-
mal watchdog timeout period and a 1.6s timeout
period immediately after reset. The reset timeout
period remains 200ms. Refer to Figure 20 .
Select alternative timeout periods by connecting
OSC SEL to ground and connecting a capacitor
between OSC IN and ground, or by externally
driving OSC IN . A synopsis of this control can
be found in Figure 21 and Table 1 .
Chip-Enable Signal Gating
The SP691A/693A/800L/800M devices
provide internal gating of chip-enable (CE)
signals, to prevent erroneous data from
corrupting the CMOS RAM in the event of a
power failure. During normal operation, the CE
gate is enabled and passes all CE transitions.
When reset is asserted, this path becomes
disabled, preventing erroneous data from
corrupting the CMOS RAM. The SP691A/
693A/800L/800M devices use a series transmission
gate from CE IN to CE OUT . Refer to Figure 16.
The 10ns maximum CE propagation from CE IN
to CE OUT enables the SP691A/693A/800L/
800M devices to be used with most μ Ps.
Chip-Enable Input
CE IN is in high impedance (disabled mode)
while RESET and/or RESET are asserted.
During a power-down sequence where V CC falls
below the reset threshold, CE IN assumes a high
impedance state when the voltage at CE IN goes
high or 12 μ s after RESET is asserted,
whichever occurs first. Refer to Figure 19 .
During a power-up sequence, CE IN remains high
impedance until RESET is deasserted.
In the high-impedance mode, the leakage
currents into CE IN are <1 μ A over temperature.
In the low-impedance mode, the impedance of
CE IN appears as a 65 ? resistor in series with
the load at CE OUT .
The propagation delay through the CE
transmission gate depends on both the source
impedance of the drive to CE IN and the
capacitive loading on CE OUT (see the
Chip-Enable Propagation Delay vs. CE OUT
Load Capacitance graph in the Typical
Performance Characteristics section ). The
CE propagation delay is defined from the 50%
point on CE IN to the 50% point on CE OUT using
a 50 ? driver and 50pF of load capacitance as in
Figure 22 . For minimum propagation delay,
minimize the capacitive load at CE OUT and use
a low output-impedance driver.
Date: 4/18/05
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over ? Copyright 2005 Sipex Corporation
13
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