参数资料
型号: SP691ACT-L
厂商: Exar Corporation
文件页数: 8/24页
文件大小: 0K
描述: IC SUPERVISOR MPU LP 16WSOIC
标准包装: 41
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极,推挽式
复位: 高有效/低有效
复位超时: 最小为 140 ms
电压 - 阀值: 4.65V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 管件
其它名称: SP691ACT-L-ND
TOP VIEW
PINOUT
Pin 7 — OSC IN — External Oscillator Input.
When OSC SEL is unconnected or driven
HIGH, a 10 μ A pull-up connects from V OUT
to this input pin, the internal oscillator sets
V BATT
V OUT
Vcc
GND
BATT ON
LOWLINE
1
2
3
4
5
6
Corporation
16 RESET
15 RESET
14 WDO
13 CE IN
12 CE OUT
11 WDI
the reset and watchdog timeout periods, and
this input pin selects between fast and slow
watchdog timeout periods. When OSC SEL is
driven LOW, the reset and watchdog timeout
periods may be set either by a capacitor from
OSC IN
OSC SEL
7
8
10
9
PFO
PFI
this input pin to ground or by an external
clock at this pin (refer to Figure 21 ).
DIP/SO
Pin 8 — OSC SEL — Oscillator Select. When
OSC SEL is unconnected or driven HIGH, the
PIN ASSIGNMENTS
Pin 1 — V BATT — Battery-Backup Input. Con-
nect to the external battery supply or super-
charging capacitor and charging circuit. If a
backup battery is not provided, connect this
pin to ground.
Pin 2 —V OUT — Output Supply Voltage. V OUT
connects to V CC when V CC is greater than
V BATT and V CC is above the reset threshold.
When V CC falls below V BATT and V CC is
below the reset threshold, V OUT connects to
V BATT . Connect a 0.1 μ F capacitor from V OUT
to GND.
Pin 3 — V CC — +5V Input Supply Voltage.
Pin 4 — GND — Ground reference for all
signals.
Pin 5 — BATT ON — Battery On Output. Goes
high when V OUT switches to V BATT . Goes low
when V OUT switches to V CC . Connect the
base of a PNP through a current-limiting
resistor to BATT ON for V OUT current
requirements greater than 250mA.
Pin 6 — LOWLINE — Low Line Output. This
output pin goes LOW when V CC falls below
the reset threshold voltage. This output pin
returns to its HIGH output as soon as V CC
rises above the reset threshold voltage.
internal oscillator sets the reset delay and
watchdog timeout period. When OSC SEL is
driven LOW, the external oscillator input
pin, OSC IN , is enabled (refer to Table 1 ).
This input pin has a 10 μ A internal pull-up.
Pin 9 — PFI — Power-Fail Input. This is the
noninverting input to the power-fail
comparator. When PFI is less than 1.25V,
PFO goes low. Connect PFI to GND or
V OUT when not used.
Pin 10 — PFO — Power-Fail Output. This is
the output of the power-fail comparator.
PFO goes low when PFI is less than 1.25V.
This is an uncommitted comparator, and
has no effect on any other internal circuitry.
Pin 11 — WDI — Watchdog Input. This is a
three-level input pin. If WDI remains either
HIGH or LOW for longer than the watchdog
timeout period, WDO goes LOW and RESET
is asserted for the reset timeout period. WDO
remains LOW until the next transition at this
input pin. Leaving this input pin unconnected
disables the watchdog function. This input
pin connects to an internal voltage divider
between V OUT and ground, which sets it to
mid-supply when left unconnected.
Date: 4/18/05
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over ? Copyright 2005 Sipex Corporation
8
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