参数资料
型号: SP691ACT-L
厂商: Exar Corporation
文件页数: 18/24页
文件大小: 0K
描述: IC SUPERVISOR MPU LP 16WSOIC
标准包装: 41
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极,推挽式
复位: 高有效/低有效
复位超时: 最小为 140 ms
电压 - 阀值: 4.65V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 管件
其它名称: SP691ACT-L-ND
+5V
160
0.1 μ F Capacitor
V CC
R 1
120
V OUT to GND
PFI
GND
PFO
R 2
V-
80
40
0
1
Above Line
Reset Generated
10 1000 10000
Reset Comparator Overdrive
5.0 - 1.25 = 1.25 - V TRIP
R 1 R 2
(Reset Threshold Voltage - V CC ), (mV)
Figure 29. Maximum Transient Duration Without
Causing a Reset Pulse vs. Reset Comparator Overdrive
PFO
+5V
As the amplitude of the transient increases
0V
*V TRIP 0V
V-
(i.e., goes farther below the reset threshold), the
maximum allowable pulse width decreases.
Typically, a V CC transient that goes 100mV
*V TRIP is a negative voltage
Figure 28. Monitoring a Negative Voltage
Negative-Going V CC Transients
While asserting resets to the μ P during power-up,
power-down, and brownout conditions, these
supervisors are relatively immune to short-
duration negative-going V CC transients. It is
usually undesirable to reset the μ P when V CC
experiences only small glitches.
Refer to Figure 29 for a graph of the maximum
transient duration vs. the reset-comparator over-
drive for which reset pulses are not generated.
The graph was produced using negative-going
pulses, starting at 5V and ending below the
reset threshold by the magnitude indicated
(reset comparator overdrive). The graph shows
the maximum pulse width a negative-going V CC
transient may typically have without causing a
reset pulse to be issued.
below the reset threshold and lasts for 40 μ s or
less will not cause a reset pulse to be issued.
A 100nF bypass capacitor mounted close to the
V CC pin provides additional transient immunity.
Connecting a Timing Capacitor to OSC IN
When OSC SEL is connected to ground, OSC IN
disconnects from its internal 10 μ A pull-up and
is internally connected to a +100nA current
source. When a capacitor is connected from
OSC IN to ground (to select an alternative
watchdog timeout period), the current source
charges and discharges the timing capacitor to
create the oscillator that controls the reset and
watchdog timeout period. To prevent timing
errors, minimize external current leakage
sources at this pin, and locate the capacitor as
close to OSC IN as possible. The sum of any PC
board leakage plus the OSC capacitor leakage
must be small compared to +100nA.
Date: 4/18/05
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over ? Copyright 2005 Sipex Corporation
18
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