12-12
DSP56853/854/855/857/858 User’s Manual
MOTOROLA
Preliminary
Functional Description
12
12.5.1.2 Normal Mode Receive
The conditions for data reception from the ESSI are as follows:
1. Set the SRXCR, SCR2, SCR3, and SCR4 registers to select Normal mode
operation.
2. Define the receive clock.
3. Receive frame sync and frame structure required for proper system operation.
4. ESSI enabled (ESSIEN = 1)
5. Enable RXFIFO (RFEN=1) and configure Receive Watermark (RFWM = n) if
RXFIFO is used.
6. Enable receive interrupts.
7. Set the RE bit (RE = 1) to enable the receiver operation on the next frame sync
boundary.
Table 12-6.
Normal Mode Transmit Operations
Step
TXFIFO Disabled1
TXFIFO Enabled
1
Rising edge of SC2. Note a word length frame
sync is shown. This only works if DC>0.
—
2
Data transferred to TXSR.
From STX
From TXFIFO
3
STD output pin is enabled2and the first bit of the
TXSR register appears on the output.
——
4
Flag status update.
The TDE bit is set
The TFE bit is set if the level of data in
the TXFIFO falls below the watermark
level.
5
If the TIE bit is set, enabling transmit interrupts,
then: Open options for processing the data
transfer is either polling or DMA transfers.
Transmit interrupt
occurs when TDE is
set.
Transmit interrupt occurs when TFE
set.
6
The TXSR is shifted on the next rising edge of
the SCK and the next bit appears on the STD
pin.
——
7
When WL bits (Section 11.8.14) have been sent
the STD is tri-stated.
——
8
Transmit underrun (setting the TUE bit of the
SSR register) is prevented by3:
New data is written
to the STX before
the TXSR tries to
obtain new transmit
data at the next
frame sync.
New data is written to the STX before
the TXSR tries to obtain data from an
empty TXFIFO (this can be several
frame times).
9
Repeat at step 1 on the next frame sync4.
——
1.
2.
The STD output signal is disabled except during the data transmission period.
3.
4.
The frame sync must not occur earlier than it is configured in the STXCR as documented in Section 12.7.11.