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DSP56853/854/855/857/858 User’s Manual
MOTOROLA
Preliminary
Register Descriptions (ITCN_BASE = $1FFF20)
8
8.7.10.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)
These values are used to declare which two IRQs will be Fast Interrupts. Fast Interrupts
vector directly to a service routine based on values in the Fast Interrupt Vector Address
registers without having to go to a jump table first. IRQs used as Fast Interrupts must be
set to priority Level 2. Unexpected results will occur if a Fast Interrupt vector is set to any
other priority. Fast Interrupts automatically become the highest priority Level 2 Interrupt
regardless of their location in the interrupt table prior to being declared as Fast Interrupt.
Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each
Figure 8-12. Fast Interrupt 1 Match Register (FIM1)
8.7.10.3 Reserved—Bits 15–7
These bits are reserved or not implemented. They are read as zero, but they cannot be
modified by writing.
8.7.10.4 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)
These values are used to declare which two IRQs will be Fast Interrupts. Fast Interrupts
vector directly to a service routine based on values in the Fast Interrupt Vector Address
registers without having to go to a jump table first. IRQs used as Fast Interrupts must be
set to priority Level 2. Unexpected results will occur if a Fast Interrupt vector is set to any
other priority. Fast Interrupts automatically become the highest priority Level 2 Interrupt
regardless of their location in the interrupt table prior to being declared as Fast Interrupt.
Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each
8.7.11 Fast Interrupt Vector Address Registers (FIVAL0, FIVAH0,
FIVAL1, FIVAH1)
The following four registers are combined to form two, 21-bit vector addresses for the
Fast Interrupts defined in the FIM0 and FIM1 registers.
$1FFF20 + $D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
FAST INTERRUPT 1
Write
RESET
0
000
00