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Register Descriptions (ESSI0_BASE = $1FFE20, ESSI1_BASE = $1FFE00)
MOTOROLA
Enhanced Synchronous Serial Interface (ESSI)
12-57
Preliminary
12
The DSP is interrupted only for enabled slots. Data written to the STX register when the
Transmitter Empty (or Transmit FIFO Empty) Interrupt Request is being serviced is
transmitted in the next enabled transmit time slot.
The TSM slot mask does not conflict with the STSR. Even if a slot is enabled in the TSM
register, the user may choose to write to the STSR to tri-state the signals of the enabled
transmitters during the next transmission slot. Setting the bits in the TSM register affects
the next frame transmission. The frame currently being transmitted is not affected by the
new TSM setting. If the TSM is read, it shows the current setting.
An ESSI reset (ESSIEN = 0) does not affect the contents of the TSM registers. After a
hardware RESET signal, or executing a DSP software RESET instruction, the TSM
register is reset to $FFFFFFFF; that value enables all 32 slots for data transmission. The
transmit DC setting determines how many of these control bits is actually used.
12.7.15 Receive Slot Mask Registers (RSMA, RSMB)
The Receive Slot Mask Registers are two 16-bit read/write registers. In the Network
mode, these registers are used by the receiver to determine which action to take in the
current time slot. Depending on the setting of the bits, the receiver either ignores the
receiver data signal(s), or receives a data word, generating the appropriate receive status.
RSMA and RSMB can be viewed as one 32-bit register, RSM. Bit n in RSM (RSMn) is an
enable/disable control bit for time slot N.
Figure 12-30. Receive Slot Mask Register (RSMA)
Figure 12-31. Receive Slot Mask Register (RSMB)
0 = Data is not transferred from the Receive Shift Register (RXSR) to the Receive
Data (SRX) register, therefore the RDR and ROE flags are not set.
BASE + $E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
RSMA[15:0]
Write
RESET
1
BASE + $F
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
RSMB[31:16]
Write
RESET
1