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JTAG Port Architecture
MOTOROLA
JTAG Port
17-9
Preliminary
17
The second function of the SAMPLE/PRELOAD instruction is to initialize the BSR
output cells (PRELOAD) prior to selection of the CLAMP or EXTEST instruction. This
initialization ensures known data appears on the outputs when executing EXTEST. The
data held in the shift register stage is transferred to the output latch on the falling edge of
TCK in the update DR controller state. Data is not presented to the pins until the CLAMP
or EXTEST instruction is executed.
Note:
Since there is no internal synchronization between the JTAG clock (TCK) and
the system clock (CLK), some form of external synchronization to achieve
meaningful results when sampling system values using the
SAMPLE/PRELOAD instruction must be provided.
17.5.1.4 TAP Linking Module Select (TLM_SEL)
TLM_SEL instruction is a user-defined JTAG instruction. It is used to disable the Master
TAP and enable the TAP Linking Module (TLM). The TLM provides a means of
connecting one or more TAPs in a multi-TAP design, responding to the IC’s test pins in
IEEE 1149.1 scan operations. TLM serves as a community data register used to set the
TAP linking configuration desired. The TLM Register is a 4-bit register, illustrated in
Figure 17-3, and enabled between TDI and TDO during a shift DR operation. It is
updated on the Update DR operation.
17.5.1.5 High Z Instruction (HIGHZ)
The HIGHZ instruction enables the single-bit bypass register between TDI and TDO. It is
provided as a public instruction in order to prevent having to drive the output signals back
during circuit board testing. When the HIGHZ instruction is invoked, all output drivers are
placed in an inactive-drive state. HIGHZ asserts internal system reset for the DSP system
logic for the duration of HIGHZ in order to force a predictable internal state while
performing external boundary scan operations.
Table 17-3. TLM Register
Update DR (Load)
Shift DR (Capture)
Bit
Master TAP
N/A
0
DSP56800E TAP
N/A
1
N/C
N/A
2
N/C
N/A
3