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参数资料
型号： SPAK56F826BU80
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 数字信号处理
英文描述： 16-BIT, 80 MHz, OTHER DSP, PQFP100
封装： LQFP-100
文件页数： 13/53页
文件大小： 829K
代理商： SPAK56F826BU80
20
DSP56F826 Preliminary Technical Data
MOTOROLA
VDD should not rise so late that a large voltage difference is allowed between the two supplies (2). Typically
this situation is avoided by using external discrete diodes in series between supplies, as shown in Figure 5.
The series diodes forward bias when the difference between VDDIO and VDD reaches approximately 1.4,
causing VDD to rise as VDDIO ramps up. When the VDD regulator begins proper operation, the difference
between supplies will typically be 0.8V and conduction through the diode chain reduces to essentially
leakage current. During supply sequencing, the following general relationship should be adhered to:
VDDIO > VDD > (VDDIO - 1.4V)
In practice, VDDA is typically connected directly to VDDIO with some filtering.
Figure 5. Example Circuit to Control Supply Sequencing
3.4 AC Electrical Characteristics
Timing waveforms in Section 3.4 are tested with a VIL maximum of 0.8V and a VIH minimum of 2.0V for
all pins except XTAL, which is tested using the input levels in Section 3.2. In Figure 6 the levels of VIH and
VIL for an input signal are shown.
Figure 6. Input Signal Measurement References
Figure 7 shows the definitions of the following signal states:
Active state, when a bus or signal is driven, and enters a low impedance state.
Tri-stated, when a bus or signal is placed in a high impedance state.
Data Valid state, when a signal level has reached VOL or VOH.
Data Invalid state, when a signal level is in transition between VOL and VOH.
3.3V
Regulator
2.5V
Regulator
Supply
VDD
VDDIO, VDDA
VIH
VIL
Fall Time
Input Signal
Note: The midpoint is VIL + (VIH – VIL)/2.
Midpoint1
Low
High
Pulse Width
90%
50%
10%
Rise Time
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