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参数资料
| 型号： | SPAK56F826BU80 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 16-BIT, 80 MHz, OTHER DSP, PQFP100 |
| 封装： | LQFP-100 |
| 文件页数： | 7/53页 |
| 文件大小： | 829K |
| 代理商： | SPAK56F826BU80 |
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Signals and Package Information
MOTOROLA
DSP56F826 Preliminary Technical Data
15
RXD1
(SS0)
92
Input
Receive Data (RXD1)— receive data input
SPI Slave Select—In maste mode, this pin is used to arbitrate
multiple masters. In slave mode, this pin is used to select the slave.
After reset, the default state is SCI input.
IRQA
32
Input
External Interrupt Request A—The IRQA input is a synchronized
external interrupt request that indicates that an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge- triggered. If level-sensitive triggering is selected, an
external pull up resistor is required for wired-OR operation.
If the processor is in the Stop state and IRQA is asserted, the
processor will exit the Stop state.
IRQB
33
Input
External Interrupt Request B—The IRQB input is an external
interrupt request that indicates that an external device is requesting
service. It can be programmed to be level-sensitive or negative-edge-
triggered. If level-sensitive triggering is selected, an external pull up
resistor is required for wired-OR operation.
RESET
45
Input
Reset—This input is a direct hardware reset on the processor. When
RESET is asserted low, the DSP is initialized and placed in the Reset
state. A Schmitt trigger input is used for noise immunity. When the
RESET pin is deasserted, the initial chip operating mode is latched
from the external boot pin. The internal reset signal will be deasserted
synchronous with the internal clocks, after a fixed number of internal
clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware DSP reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.
EXTBOOT
25
Input
External Boot—This input is tied to VDD to force device to boot from
off-chip memory. Otherwise, it is tied to ground.
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
Signal
Name
Pin No.
Type
Description
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| SPAKDSP303GC100 | 制造商:Motorola Inc 功能描述: |
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| SPAKDSP303VL100 | 功能描述:IC DSP 24BIT 100MHZ 196-MAPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:DSP563xx 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
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