参数资料
型号: SPC5604PGF0MLL6
厂商: Freescale Semiconductor
文件页数: 14/104页
文件大小: 0K
描述: IC MCU 32BIT 512KB FLASH 100LQFP
标准包装: 90
系列: MPC56xx Qorivva
核心处理器: e200z0h
芯体尺寸: 32-位
速度: 64MHz
连通性: CAN,FlexRay,LIN,SPI,UART/USART
外围设备: DMA,POR,PWM,WDT
输入/输出数: 68
程序存储器容量: 512KB(512K x 8)
程序存储器类型: 闪存
EEPROM 大小: 64K x 8
RAM 容量: 40K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 30x10b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 100-LQFP
包装: 托盘
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
17
— Input capture trigger
— Output compare
— Double buffer (to capture rising edge and falling edge)
— Separate prescaler for each counter
— Selectable clock source
— 0–100% pulse measurement
— Rotation direction flag (Quad decoder mode)
Maximum count rate
— External event counting: max. count rate = peripheral clock/2
— Internal clock counting: max. count rate = peripheral clock
Counters are:
— Cascadable
— Preloadable
Programmable count modulo
Quadrature decode capabilities
Counters can share available input pins
Count once or repeatedly
Pins available as GPIO when timer functionality not in use
1.5.27
Analog-to-digital converter (ADC) module
The ADC module provides the following features:
Analog part:
2 on-chip AD converters
— 10-bit AD resolution
— 1 sample and hold unit per ADC
— Conversion time, including sampling time, less than 1 s (at full precision)
— Typical sampling time is 150 ns min. (at full precision)
— Differential non-linearity error (DNL) ±1 LSB
— Integral non-linearity error (INL) ±1.5 LSB
—TUE <3 LSB
— Single-ended input signal up to 5.0 V
— The ADC and its reference can be supplied with a voltage independent from VDDIO
— The ADC supply can be equal or higher than VDDIO
— The ADC supply and the ADC reference are not independent from each other (they are internally bonded to the
same pad)
— Sample times of 2 (default), 8, 64, or 128 ADC clock cycles
Digital part:
2 × 13 input channels including 4 channels shared between the 2 converters
4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in
the appropriate ADC result location,
2 modes of operation: Normal mode or CTU control mode
Normal mode features
— Register-based interface with the CPU: control register, status register, 1 result register per channel
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