MPC5634M Microcontroller Data Sheet, Rev. 6
Overview
Freescale Semiconductor
10
— External Hardware Triggers
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Supports rising edge, falling edge, high level and low level triggers
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Supports configurable digital filter
— Supports four external 8-to-1 muxes which can expand the input channel number from 31 to 59
Two deserial serial peripheral interface modules (DSPI)
—SPI
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Full duplex communication ports with interrupt and DMA request support
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Supports all functional modes from QSPI subblock of QSMCM (MPC5xx family)
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Support for queues in RAM
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6 chip selects, expandable to 64 with external demultiplexers
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Programmable frame size, baud rate, clock delay and clock phase on a per frame basis
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Modified SPI mode for interfacing to peripherals with longer setup time requirements
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LVDS option for output clock and data to allow higher speed communication
— Deserial serial interface (DSI)
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Pin reduction by hardware serialization and deserialization of eTPU, eMIOS channels and GPIO
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32 bits per DSPI module
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Triggered transfer control and change in data transfer control (for reduced EMI)
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Compatible with Microsecond Bus Version 1.0 downlink
Two enhanced serial communication interface (eSCI) modules
— UART mode provides NRZ format and half or full duplex interface
— eSCI bit rate up to 1 Mbps
— Advanced error detection, and optional parity generation and detection
— Word length programmable as 8, 9, 12 or 13 bits
— Separately enabled transmitter and receiver
— LIN support
— DMA support
— Interrupt request support
— Programmable clock source: system clock or oscillator clock
— Support Microsecond Bus (Timed Serial Bus - TSB) uplink Version 1.0
Two FlexCAN
— One with 32 message buffers; the second with 64 message buffers
— Full implementation of the CAN protocol specification, Version 2.0B
— Based on and including all existing features of the Freescale TouCAN module
— Programmable acceptance filters
— Short latency time for high priority transmit messages
— Arbitration scheme according to message ID or message buffer number
— Listen only mode capabilities
— Programmable clock source: system clock or oscillator clock
— Message buffers may be configured as mailboxes or as FIFO
Nexus port controller (NPC)
— Per IEEE-ISTO 5001-2003
— Real time development support for Power Architecture core and eTPU engine through Nexus class 2/1
— Read and write access (Nexus class 3 feature that is supported on this device)
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Run-time access of entire memory map
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Calibration