参数资料
型号: SPC5632MF0MLQA6
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: FLASH, 60 MHz, MICROCONTROLLER, PQFP144
封装: 20 X 20 MM, 0.50 MM PITCH, 1.40 HEIGHT, ROHS COMPLIANT, LQFP-144
文件页数: 38/122页
文件大小: 1173K
代理商: SPC5632MF0MLQA6
MPC5634M Microcontroller Data Sheet, Rev. 6
Overview
Freescale Semiconductor
22
Combined serial interface (CSI) configuration where the DSPI operates in both SPI and DSI configurations
interleaving DSI frames with SPI frames, giving priority to SPI frames
For queued operations, the SPI queues reside in system memory external to the DSPI. Data transfers between the memory and
the DSPI FIFOs are accomplished through the use of the eDMA controller or through host software.
The DSPI supports these SPI features:
Full-duplex, synchronous transfers
Selectable LVDS Pads working at 40 MHz for SOUT, SIN and SCK pins
Master and Slave Mode
Buffered transmit operation using the TX FIFO with parameterized depth of 1 to 16 entries
Buffered receive operation using the RX FIFO with parameterized depth of 1 to 16 entries
TX and RX FIFOs can be disabled individually for low-latency updates to SPI queues
Visibility into the TX and RX FIFOs for ease of debugging
FIFO Bypass Mode for low-latency updates to SPI queues
Programmable transfer attributes on a per-frame basis:
— Parameterized number of transfer attribute registers (from two to eight)
— Serial clock with programmable polarity and phase
— Various programmable delays:
PCS to SCK delay
–SCK to PCS delay
Delay between frames
— Programmable serial frame size of 4 to 16 bits, expandable with software control
— Continuously held chip select capability
6 Peripheral Chip Selects, expandable to 64 with external demultiplexer
Deglitching support for up to 32 Peripheral Chip Selects with external demultiplexer
DMA support for adding entries to TX FIFO and removing entries from RX FIFO:
— TX FIFO is not full (TFFF)
— RX FIFO is not empty (RFDF)
6 Interrupt conditions:
— End of queue reached (EOQF)
— TX FIFO is not full (TFFF)
— Transfer of current frame complete (TCF)
— Attempt to transmit with an empty Transmit FIFO (TFUF)
— RX FIFO is not empty (RFDF)
— FIFO Underrun (slave only and SPI mode, the slave is asked to transfer data when the TxFIFO is empty)
— FIFO Overrun (serial frame received while RX FIFO is full)
Modified transfer formats for communication with slower peripheral devices
Continuous Serial Communications Clock (SCK)
Power savings via support for Stop Mode
Enhanced DSI logic to implement a 32-bit Timed Serial Bus (TSB) configuration, supporting the Microsecond Bus
downstream frame format
The DSPIs also support these features unique to the DSI and CSI configurations:
2 sources of the serialized data:
— eTPU_A and eMIOS output channels
— Memory-mapped register in the DSPI
Destinations for the deserialized data:
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