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MPC5634M Microcontroller Data Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor
76
3.9
I/O Pad current specifications
NOTE
MPC5634M devices use two sets of I/O pads (5 V and 3.3 V). See
Table 1 and
Table 4 in
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption
is the sum of all output pin currents for a particular segment. The output pin current can be calculated from
Table 20 based on
8 V
FLASH is only available in the calibration package.
9 Regulator is functional, with derated performance, with supply voltage down to 4.0 V.
10 Multi-voltage pads (type pad_multv_hv) must be supplied with a power supply between 4.75 V and 5.25 V.
11 The slew rate (SRC) setting must be 0b11 when in low-swing mode.
12 While in low-swing mode there are no restrictions in transitioning to high-swing mode.
13 Pin in low-swing mode can accept a 5 V input.
14 Values are pending characterization.
15 Pin in low-swing mode can accept a 5 V input.
16 Characterization based capability:
IOH_S = {6, 11.6} mA and IOL_S = {9.2, 17.7} mA for {slow, medium} I/O with VDDEH=4.5 V;
IOH_S = {2.8, 5.4} mA and IOL_S = {4.2, 8.1} mA for {slow, medium} I/O with VDDEH=3.0 V
17 Characterization based capability:
IOH_F = {12, 20, 30, 40} mA and IOL_F = {24, 40, 50, 65} mA for {00, 01,10, 11} drive mode with VDDE=3.0 V;
IOH_F = {7, 13, 18, 25} mA and IOL_F = {18, 30, 35, 50} mA for {00, 01, 10, 11} drive mode with VDDE=2.25 V;
IOH_F = {3, 7, 10, 15} mA and IOL_F = {12, 20, 27, 35} mA for {00, 01, 10, 11} drive mode with VDDE=1.62 V
18 All VOL/VOH values 100% tested with ± 2 mA load.
19 Run mode as follows:
System clock = 40/60/80 MHz + FM 2%
Code executed from flash memory
ADC0 at 16 MHz with DMA enabled
ADC1 at 8 MHz
eMIOS pads toggle in PWM mode with a rate between 100 kHz and 500 kHz
eTPU pads toggle in PWM mode with a rate between 10 kHz and 500 kHz
CAN configured for a bit rate of 500 kHz
DSPI configured in master mode with a bit rate of 2 MHz
eSCI transmission configured with a bit rate of 100 kHz
20 Bypass mode, system clock at 1 MHz (using system clock divider), PLL shut down, CPU running simple executive code,
4 x ADC conversion every 10 ms, 2 x PWM channels at 1 kHz, all other modules stopped.
21 Bypass mode, system clock at 1 MHz (using system clock divider), CPU stopped, PIT running, all other modules stopped.
22 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a
particular I/O segment, and the voltage of the I/O segment. See
Table 20 for values to calculate power dissipation for
specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for
each pin on the segment.
23 Absolute value of current, measured at V
IL and VIH.
24 Weak pull up/down inactive. Measured at V
DDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types: fast (pad_fc).
25 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for
each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: pad_a and pad_ae.
26 Applies to CLKOUT, external bus pins, and Nexus pins.
27 Applies to the FCK, SDI, SDO, and SDS pins.
28 This programmable option applies only to eQADC differential input channels and is used for biasing and sensor
diagnostics.
29 When the pull-up and pull-down of the same nominal 200 K
Ω or 100 KΩ value are both enabled, assuming no interference
from external devices, the resulting pad voltage will be 0.5*VDDE ±2.5%