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| 型号： | SPEAR-09-P022 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 1000M bps, I2C BUS CONTROLLER, PBGA420 |
| 封装： | 23 X 23 MM, 1.81 MM HEIGHT, ROHS COMPLIANT, PLASTIC, BGA-420 |
| 文件页数： | 18/40页 |
| 文件大小： | 328K |
| 代理商： | SPEAR-09-P022 |
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SPEAR-09-P022
Main blocks
4
Main blocks
4.1
7.1 CPU subsystem
4.1.1
Overview
Each CPU sub-system includes the following blocks:
●
ARM 926EJS
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Two timer channels
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One GPIO block (8 I/O lines)
●
Two interrupt controller (32 IRQ lines)
4.1.2
CPU ARM 926EJ-S
The processor is the powerful ARM926EJ-S, targeted for multi-tasking applications.
Belonging to ARM9 general purposes family microprocessor, it principally stands out for the
memory management unit, which provides virtually memory features, making it also
compliant with WindowsCE, linux and SymbianOS operating systems.
The ARM926EJ-S supports the 32-bit ARM and 16-bit thumb instruction sets, enabling the
user to trade off between high performance and high code density and includes features for
efficient execution of java byte codes.
Besides, it has the ARM debug architecture and includes logic to assist in software debug.
Its main features are:
●
Core fMAX 333 MHz independent programmable for each CPU
●
Memory management unit
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16 Kbyte of instruction cache
●
16 Kbyte of data cache
●
Configurable tightly coupled memory (I/D) size trough the configurable logic array
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ARM-V5TEJ instructions set architecture:
–
ARM (32-bit), thumb (16-bit)
–
DSP extensions
–
JAVA (8-bit) instructions
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AMBA bus interface
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Coprocessor interface (only for the 1st processor)
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EmbeddedICE-RT
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Single mode (two connectors)
–
Two processor daisy chained
●
ETM9 (embedded trace macro-cell)
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Single ETM mode (single or double packet configurable)
–
Dual ETM mode (both processors ETM are available in single packet mode)
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