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参数资料
| 型号： | SPEAR-09-P022 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 1000M bps, I2C BUS CONTROLLER, PBGA420 |
| 封装： | 23 X 23 MM, 1.81 MM HEIGHT, ROHS COMPLIANT, PLASTIC, BGA-420 |
| 文件页数： | 25/40页 |
| 文件大小： | 328K |
| 代理商： | SPEAR-09-P022 |
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SPEAR-09-P022
Main blocks
4.9
Reconfigurable logic array
4.9.1
Overview
The configurable logic array consists of an embedded macro where it is possible to
implement a custom project by mapping up to 600 K equivalent gates.
This macro is interfaced with the rest of the system by some AHB bus, some memory
channels and has a direct connection to the 1st ARM processor internal bus. In this way is
also possible to customize the TCM memory or add a coprocessor using this macro.
The following memory cuts are available to this block:
●
4 cuts single port with size of 8 Kbyte each
●
8 cuts single port with size of 4 Kbyte each
●
16 cuts single port with size of 2 Kbyte each
●
8 cuts dual port with size of 2 Kbyte each
●
4 cuts dual port with size of 4 Kbyte each
The array is also connected to 88 I/O (3.3 V capable/tolerant and 4 mA sink/source) plus 9
lvds lines (one input and 8 outputs).
The following clocks can be used in the integrated logic:
●
5 different coming from the external balls
●
4 different coming from the integrated frequency synthesizer
●
PLL1 frequency
●
PLL2 frequency
●
48 MHz (USB PLL)
●
30 MHZ (MAIN oscillator)
●
32.768 KHz (RTC oscillator)
●
APB clock (programmable)
●
AHB clock (programmable)
4.9.2
Custom project development
The flow to develop a custom project to embed in the SPEAr Plus600 is similar to the
standard ASIC flow.
The configurable logic is an empty module of the whole system-on-chip. Pin out and
maximum gates are fixed. The HDL project is synthesized using dedicated library and post
synthesis simulation is possible to verify the custom net-list.
Regarding the back end flow, after the place and route phase the verification procedure is
the same as a standard ASIC flow.
4.9.3
Customization process
The layers used for the IP configuration range from 2 metals - 1 via up to 4 metals - 4 vias.
Diffusion and remaining metal/vias are invariant across multiple custom designs. Density
and performance scale with number of customization layers.
The configurable logic included in the SPEAr Plus600 chip is a 600 Kgates equivalent array
when customized using 4 metals - 4 vias.
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