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参数资料
| 型号： | SPEAR-09-P022 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 1000M bps, I2C BUS CONTROLLER, PBGA420 |
| 封装： | 23 X 23 MM, 1.81 MM HEIGHT, ROHS COMPLIANT, PLASTIC, BGA-420 |
| 文件页数： | 19/40页 |
| 文件大小： | 328K |
| 代理商： | SPEAR-09-P022 |
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Main blocks
SPEAR-09-P022
4.2
Clock and reset system
The clock system block is a fully programmable block able to generate all clocks necessary
at the chip.
The clocks, at default operative frequency, are:
●
Clock @ 333 MHz for the CPUs (Note 1)
●
Clock @ 166 MHz for AHB bus and AHB peripherals (Note 1)
●
Clock @ 83 MHz for, APB bus and APB peripherals (Note 1)
●
Clock @ 100-333 MHz for DDR memory interface (Note 2)
The frequencies are the maximum allowed value and the user can modify them by
programming dedicated registers.
The clock system consists of 2 main parts: a multi-clock generator block and an two internal
PLL.
The multi-clock generator block, starting from a reference signal (which generally is
delivered from the PLL), generates all clocks for the IPs of SPEAr Plus600 according to
dedicated programmable registers.
Each PLL, starting from the oscillator input of 30 MHz, generates a clock signal at a
frequency corresponding at the highest of the group, which is the reference signal used by
the multi-clock generator block to obtain all the other requested clocks for the group. Its main
features is the electro-magnetic interference reduction capability: user has the possibility to
set up the PLL in order to modulate with a triangular wave to the VCO clock, the resulting
signal will have the spectrum (and the power) spread on a small range (programmable) of
frequencies centered on F0 (VCO Freq.), obtaining minimum electromagnetic emissions.
This method replace all the other traditional methods of E.M.I. reduction, as filtering, ferrite
beads, chokes, adding power layers and ground planets to PCBs, metal shielding etc.,
allowing sensible cost saving for customers.
Note:
1
This frequency is based on the PLL1.
2
This frequency is based on the PLL2.
4.3
Main oscillator
4.3.1
Crystal connection
Figure 3.
Crystal connection
VDD2V5
33 pF
30 MHz
Xi
Xo
33 pF
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