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参数资料
| 型号： | SPEAR-09-P022 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 1000M bps, I2C BUS CONTROLLER, PBGA420 |
| 封装： | 23 X 23 MM, 1.81 MM HEIGHT, ROHS COMPLIANT, PLASTIC, BGA-420 |
| 文件页数： | 22/40页 |
| 文件大小： | 328K |
| 代理商： | SPEAR-09-P022 |
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SPEAR-09-P022
Main blocks
4.5
Ethernet controller
●
Compliant with the IEEE 802.3-2002 standard
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GMII or MII interface to the external PHY
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It supports 10/100/1000 Mbps data transfer rates with any one or a combination of the
PHY interfaces above
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Local FIFO available (4 Kbyte RX, 2 Kbyte TX)
●
It supports both half-duplex and full-duplex operation. In half-duplex operation,
CSMA/CD protocol is provided for, as well as packet bursting and frame extension at
1000 Mbps
●
Programmable frame length to support both standard and jumbo ethernet frames with
size up to 16 Kbytes
●
A variety of flexible addresses filtering modes are supported
●
A set of control and status registers (CSRs) to control GMAC core operation
●
Native DMA with single-channel transmit and receive engines, providing 32/64/128-bit
data transfers
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DMA implements dual-buffer (ring) or linked-list (chained) descriptor chaining
●
An AHB slave acting as programming interface to access all CSRs, for both DMA and
GMAC core subsystems
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An AHB master for data transfer to system memory
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32-bit AHB master bus width, supporting 32, 64, and 128-bit wide data transactions
4.6
USB2 host controller
SPEAr Plus600 has two fully independent USB 2.0 hosts and each one is constituted with 5
major blocks:
●
EHCI able to manage the high speed transfer (HS - 480 Mbit)
●
OHCI that manages the full and the low speed transfer (12 and 1.5 Mbit)
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Local FIFO having size of 2 Kbyte
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Local DMA
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Integrated USB2 transceiver (PHY)
Both the hosts are capable to manage an external power switch providing the control line to
enable or disable the power and also having an input line to sense the over-current condition
detected by the external switch.
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