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参数资料
| 型号： | SPEAR-09-P022 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 1000M bps, I2C BUS CONTROLLER, PBGA420 |
| 封装： | 23 X 23 MM, 1.81 MM HEIGHT, ROHS COMPLIANT, PLASTIC, BGA-420 |
| 文件页数： | 39/40页 |
| 文件大小： | 328K |
| 代理商： | SPEAR-09-P022 |
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Product overview
SPEAR-09-P022
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ADC (1 s/1MSPS) 8 analog input channel, 10-bit approximation
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JPEG codec accelerator 1clock/pixel
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10 independent timers with programmable prescaler
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RTC - WDOG - SYSCTR - MISC internal control registers
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JTAG (IEEE1149.1) interface
1.2
Architecture properties
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Dual symmetric processor architecture:
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All internal peripherals are shared, allowing flexible and efficient SW partitions
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High throughput can be sustained in aggregate way splitting critical tasks either
onto additional CPUs and optional HW accelerators engines
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Critical resources are private to each CPU (interrupt controller and OS timers)
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Both processors are equipped with ICE and ETM configurable debug interfaces
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Power save features:
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Operating frequency SW programmable
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Clock gating functionality
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Low frequency operating mode
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Automatic power saving controlled from application activity demands
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Customizable logic to embed the customer real 'core competence':
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600Kgate standard cell array
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Internal memory pool (128 Kbyte) full configurable
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Up to 16 external/internal source clock (some of these programmable)
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Three memory path toward the SDRAM controller to ensure a good bandwidth
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Architecture easily extensible
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External memory bandwidth of each master tuneable to meet the target performances
of different applications
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