MC68336/376
TIME PROCESSOR UNIT
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
11-13
pulses on the rising or falling edge. This function is intended for high speed measure-
ment; measurement of slow pulses with noise rejection can be made with PTA.
Refer to TPU programming note Frequency Measurement (FQM) TPU Function
(TPUPN03/D) for more information.
11.5.10 Hall Effect Decode (HALLD)
This function decodes the sensor signals from a brushless motor, along with a direc-
tion input from the CPU32, into a state number. The function supports two- or three-
sensor decoding. The decoded state number is written into a COMM channel, which
outputs the required commutation drive signals. In addition to brushless motor appli-
cations, the function can have more general applications, such as decoding option
switches.
Refer to TPU programming note Hall Effect Decode (HALLD) TPU Function
(TPUPN10/D) for more information.
11.6 Host Interface Registers
The TPU memory map contains three groups of registers:
System configuration registers
Channel control and status registers
Development support and test verification registers
All registers except the channel interrupt status register (CISR) must be read or written
by means of word accesses. The address space of the TPU memory map occupies
512 bytes. Unused registers within the 512-byte address space return zeros when
read.
11.6.1 System Configuration Registers
The TPU configuration control registers, TPUMCR and TICR, determine the value of
the prescaler, perform emulation control, specify whether the external TCR2 pin func-
tions as a clock source or as gate of the DIV8 clock for TCR2, and determine interrupt
information about TPUMCR and TICR.
11.6.1.1 Prescaler Control for TCR1
Timer count register one (TCR1) is clocked from the output of a prescaler. Two fields
in TPUMCR control TCR1. The prescaler's input is the internal TPU system clock
divided by either 4 or 32, depending on the value of the PSCK bit. The prescaler
divides this input by 1, 2, 4, or 8, depending on the value of TCR1P. Channels using
TCR1 have the capability to resolve down to the TPU system clock divided by 4. Refer