MC68336/376
CENTRAL PROCESSOR UNIT
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
4-10
tion. Exception processing can be forced externally by an interrupt, a bus error, or a
reset.
The halted processing state is an indication of catastrophic hardware failure. For
example, if during the exception processing of a bus error another bus error occurs,
the processor assumes that the system is unusable and halts.
The background processing state is initiated by breakpoints, execution of special
instructions, or a double bus fault. Background processing is enabled by pulling BKPT
low during RESET. Background processing allows interactive debugging of the system
via a simple serial interface.
4.7 Privilege Levels
The processor operates at one of two levels of privilege: user or supervisor. Not all
instructions are permitted to execute at the user level, but all instructions are available
at the supervisor level. Effective use of privilege level can protect system resources
from uncontrolled access. The state of the S bit in the status register determines the
privilege level and whether the user stack pointer (USP) or supervisor stack pointer
(SSP) is used for stack operations.
4.8 Instructions
The CPU32 instruction set is summarized in Table 4-2. The instruction set of the
CPU32 is very similar to that of the MC68020. Two new instructions have been added
to facilitate controller applications: low-power stop (LPSTOP) and table lookup and
interpolate (TBLS, TBLSN, TBLU, TBLUN).
Table 4-1 shows the MC68020 instructions that are not implemented on the CPU32.
The CPU32 traps on unimplemented instructions or illegal effective addressing
modes, allowing user-supplied code to emulate unimplemented capabilities or to
define special purpose functions. However, Motorola reserves the right to use all cur-
rently
unimplemented
instruction
operation
codes
for
future
M68000
core
enhancements.
Table 4-1 Unimplemented MC68020 Instructions
BFxx
Bit Field Instructions
(BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST)
CALLM, RTM
Call Module, Return Module
CAS, CAS2
Compare and Swap (Read-Modify-Write Instructions)
cpxxx
Coprocessor Instructions (cpBcc, cpDBcc, cpGEN)
PACK, UNPK
Pack, Unpack BCD Instructions
Memory
Memory Indirect Addressing Modes