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参数资料
| 型号： | SST25VF010A-33-4I-ZAE |
| 厂商： | Microchip Technology |
| 文件页数： | 9/28页 |
| 文件大小： | 0K |
| 描述： | IC FLASH SER 1MB 33MHZ SPI 8CSP |
| 标准包装： | 3,000 |
| 系列： | SST25 |
| 格式 - 存储器： | 闪存 |
| 存储器类型： | FLASH |
| 存储容量： | 1M (128K x 8) |
| 速度： | 33MHz |
| 接口： | SPI 串行 |
| 电源电压： | 2.7 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-UFBGA，CSPBGA |
| 供应商设备封装： | 8-CSP |
| 包装： | 管件 |
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1 Mbit SPI Serial Flash
A Microchip Technology Company
SST25VF010A
Data Sheet
Instructions
Instructions are used to Read, Write (Erase and Program), and configure the SST25VF010A. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut-
ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or
Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list
of the instructions is provided in Table 6. All instructions are synchronized off a high to low transition of
CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must
be driven low before an instruction is entered and must be driven high after the last bit of the instruction
has been shifted in (except for Read, Read-ID and Read-Status-Register instructions). Any low to high
transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction
in progress and return the device to the standby mode. Instruction commands (Op Code), addresses,
and data are all input from the most significant bit (MSB) first.
Table 6: Device Operation Instructions 1
Bus Cycle 2
1
2
3
4
5
6
Cycle Type/
S I
S I
Operation 3,4
Read (20 MHz)
S IN
03H
S OUT
Hi-Z
S IN
A 23 -
S OUT
Hi-Z
S IN
A 15 -
S OUT
Hi-Z
S IN
A 7 -A 0
S OUT
Hi-Z
N
X
S OUT
D OUT
N
S OUT
A 16
A 8
High-Speed-Read (33
0BH
Hi-Z
A 23 -
Hi-Z
A 15 -
Hi-Z
A 7 -A 0
Hi-Z
X
X
X
D OUT
MHz)
A 16
A 8
Sector-Erase 5,6
20H
Hi-Z
A 23 -
Hi-Z
A 15 -
Hi-Z
A 7 -A 0
Hi-Z
-
-
A 16
A 8
Block-Erase 5,7
52H
Hi-Z
A 23 -
Hi-Z
A 15 -
Hi-Z
A 7 -A 0
Hi-Z
-
-
or
D8H
A 16
A 8
Chip-Erase 6
60H
Hi-Z
-
-
-
-
-
-
-
-
or
C7H
Byte-Program 6
02H
Hi-Z
A 23 -
Hi-Z
A 15 -
Hi-Z
A 7 -A 0
Hi-Z
D IN
Hi-Z
Hi-Z
A 16
A 8
Auto Address Increment
(AAI) Program 6,8
Read-Status-Register
(RDSR)
Enable-Write-Status-Regis-
AFH
05H
50H
Hi-Z
Hi-Z
Hi-Z
A 23 -
A 16
X
-
Hi-Z
D OUT
-
A 15 -
A 8
-
-
Hi-Z
Note
9
-
A 7 -A 0
-
-
Hi-Z
Note
9
-
D IN
-
-
Hi-Z
Note 9
-
Hi-Z
Note 9
ter
(EWSR) 10
Write-Status-Register
01H
Hi-Z
Data
Hi-Z
-
-
-.
-
-
-
(WRSR) 10
Write-Enable (WREN)
Write-Disable (WRDI)
06H
04H
Hi-Z
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Read-ID
90H
or
Hi-Z
00H
Hi-Z
00H
Hi-Z
ID
Addr 11
Hi-Z
X
D OUT
12
D OUT1
2
ABH
T6.0 25081
1. A MS = Most Significant Address
A MS = A 16 for SST25VF010A
Address bits above the most significant bit of each density can be V IL or V IH
2. One bus cycle is eight clock periods.
3. Operation: S IN = Serial In, S OUT = Serial Out
4. X = Dummy Input Cycles (V IL or V IH ); - = Non-Applicable Cycles (Cycles are not necessary)
5. Sector addresses: use A MS -A 12 , remaining addresses can be V IL or V IH
?2011 Silicon Storage Technology, Inc.
9
S725081A
10/11
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