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参数资料
| 型号： | SST25WF512-40-5I-SAF |
| 厂商： | Microchip Technology |
| 文件页数： | 13/36页 |
| 文件大小： | 0K |
| 描述： | IC FLASH SER 512K 40MH SPI 8SOIC |
| 标准包装： | 100 |
| 系列： | SST25 |
| 格式 - 存储器： | 闪存 |
| 存储器类型： | FLASH |
| 存储容量： | 512K (64K x 8) |
| 速度： | 40MHz |
| 接口： | SPI 串行 |
| 电源电压： | 1.65 V ~ 1.95 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
A Microchip Technology Company
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SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Data Sheet
One bus cycle is eight clock periods.
Address bits above the most significant bit of each density can be V IL or V IH .
4 KByte Sector-Erase addresses: use A MS -A 12, remaining addresses are don’t care but must be set either at V IL or V IH.
32 KByte Block-Erase addresses: use A MS -A 15, remaining addresses are don’t care but must be set either at V IL or V IH.
64 KByte Block-Erase addresses: use A MS -A 16, remaining addresses are don’t care but must be set either at V IL or V IH.
To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of
data to be programmed. Data Byte 0 will be programmed into the initial address [A 23 -A 1 ] with A 0 =0, Data Byte 1 will be
programmed into the
initial address [A 23 -A 1 ] with A 0 = 1.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
8. Either EWSR or WREN followed by WRSR will write to the Status register. The EWSR-WRSR sequence provides back-
ward compatibility to the SST25VF/LF series. The WREN-WRSR sequence is recommended for new designs.
9. Manufacturer’s ID is read with A 0 =0, and Device ID is read with A 0 =1. All other address bits are 00H. The Manufac-
turer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
Read (20 MHz)
The Read instruction, 03H, supports up to 20 MHz Read. The device outputs a data stream starting
from the specified address location. The data stream is continuous through all addresses until termi-
nated by a low-to-high transition on CE#. The internal address pointer automatically increments until
the highest memory address is reached. Once the highest memory address is reached, the address
pointer automatically increments to the beginning (wrap-around) of the address space. For example,
for 2 Mbit density, once the data from the address location 3FFFFH is read, the next output is from
address location 000000H. The Read instruction is initiated by executing an 8-bit command, 03H, fol-
lowed by address bits A 23 -A 0 . CE# must remain active low for the duration of the Read cycle. See Fig-
ure 6 for the Read sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47
48
55 56
63 64
70
SCK
MODE 0
SI
03
ADD.
ADD.
ADD.
SO
MSB
MSB
HIGH IMPEDANCE
N
D OUT
N+1
D OUT
N+2
D OUT
N+3
D OUT
N+4
D OUT
MSB
1328 Fx6.0
Figure 6: Read Sequence
?2011 Silicon Storage Technology, Inc.
13
DS25016A
06/11
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