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参数资料
| 型号： | SST25WF512-40-5I-SAF |
| 厂商： | Microchip Technology |
| 文件页数： | 18/36页 |
| 文件大小： | 0K |
| 描述： | IC FLASH SER 512K 40MH SPI 8SOIC |
| 标准包装： | 100 |
| 系列： | SST25 |
| 格式 - 存储器： | 闪存 |
| 存储器类型： | FLASH |
| 存储容量： | 512K (64K x 8) |
| 速度： | 40MHz |
| 接口： | SPI 串行 |
| 电源电压： | 1.65 V ~ 1.95 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
A Microchip Technology Company
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Data Sheet
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-
Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any com-
mand sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, fol-
lowed by address bits [A 23 -A 0 ]. Address bits [A MS -A 12 ] (A MS = Most Significant address) are used to
determine the sector address (SA X ), remaining address bits can be V IL or V IH. CE# must be driven high
before the instruction is executed. The user may poll the Busy bit in the software status register or wait
T SE for the completion of the internal self-timed Sector-Erase cycle. See Figure 13 for the Sector-
Erase sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31
SCK
MODE 0
SI
20
ADD.
ADD.
ADD.
SO
MSB
MSB
HIGH IMPEDANCE
1326 F13.0
Figure 13: Sector-Erase Sequence
32-KByte Block-Erase
The Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area is ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must remain active low for the duration of any command
sequence. The Block-Erase instruction is initiated by executing an 8-bit command, 52H, followed by
address bits [A 23 -A 0 ]. Address bits [A MS -A 15 ] (A MS = Most Significant Address) are used to determine
block address (BA X ), remaining address bits can be V IL or V IH. CE# must be driven high before the instruc-
tion is executed. Poll the Busy bit in the software status register or wait T BE for the completion of the inter-
nal self-timed Block-Erase. See Figure 14 for the Block-Erase sequences.
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31
SCK
MODE 0
SI
52
ADDR
ADDR
ADDR
SO
MSB
MSB
HIGH IMPEDANCE
1328 F14.0
Figure 14: 32-KByte Block-Erase Sequence
?2011 Silicon Storage Technology, Inc.
18
DS25016A
06/11
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