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参数资料
| 型号： | SST32HF1621C-90-4C-LS |
| 厂商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分类： | 存储器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA62 |
| 封装： | 8 X 10 MM, 1.40 MM HEIGHT, MO-210, LFBGA-62 |
| 文件页数： | 13/37页 |
| 文件大小： | 451K |
| 代理商： | SST32HF1621C-90-4C-LS |
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20
Preliminary Specifications
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481
SST32HF1621C / SST32HF1641C / SST32HF3241C
2004 Silicon Storage Technology, Inc.
S71236-02-000
6/04
FIGURE 11: FLASH TOGGLE BIT TIMING DIAGRAM
FIGURE 12: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM
1236 F10.1
ADDRESSES AMSF-0
DQ6 and DQ2
WE#
OE#
BEF#
TOE
TOEH
TCE
TOES
TWO READ CYCLES
WITH SAME OUTPUTS
Note: AMSF = Most Significant Flash Address
AMSF = A19 for SST32HF16x1x, A20 for SST32HF32x1x, and A21 for SST32HF6481
1236 F11.2
ADDRESS AMS-0
DQ15-0
WE#
SW0
SW1
SW2
SW3
SW4
SW5
5555
2AAA
5555
XX55
XX10
XX55
XXAA
XX80
XXAA
5555
OE#
BEF#
SIX-BYTE CODE FOR CHIP-ERASE
TSCE
TWP
Note: AMSF = Most Significant Flash Address
AMSF = A19 for SST32HF16x1x, A20 for SST32HF32x1x, and A21 for SST32HF6481
WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence
This device also supports BEF# controlled Chip-Erase operation.
The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 13)
X can be VIL or VIH, but no other value.
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相关代理商/技术参数 |
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| SST32HF1622C | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:Multi-Purpose Flash Plus + SRAM ComboMemory |
| SST32HF1622C-70-4C-LFS | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:Multi-Purpose Flash Plus + SRAM ComboMemory |
| SST32HF1622C-70-4C-LFSE | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:Multi-Purpose Flash Plus + SRAM ComboMemory |
| SST32HF1622C-70-4C-LS | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:Multi-Purpose Flash Plus + SRAM ComboMemory |
| SST32HF1622C-70-4C-LSE | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:Multi-Purpose Flash Plus + SRAM ComboMemory |
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