参数资料
型号: SST55LD017C-40-I-TQW
厂商: SILICON STORAGE TECHNOLOGY INC
元件分类: 存储控制器/管理单元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PQFP100
封装: MS-026AED, TQFP-100
文件页数: 10/52页
文件大小: 606K
代理商: SST55LD017C-40-I-TQW
18
EOL Product Data Sheet
ATA Flash Disk Controller
SST55LD017A / SST55LD017B / SST55LD017C
2006 Silicon Storage Technology, Inc.
S71211-03-EOL
4/06
10.1.2.9 Status & Alternate Status Registers (Read Only) (See Table 10-1 for register addressing)
These registers return the ATA flash disk controller status when read by the host. Reading the Status register does
clear a pending interrupt while reading the Alternate Status register does not. The meaning of the status bits are
described as follows:
Symbol
Function
BUSY
The busy bit is set when the ATA flash disk controller has access to the command buffer
and registers and the host is locked out from accessing the command register and buffer.
No other bits in this register are valid when this bit is set to a 1.
RDY
RDY indicates whether the device is capable of performing ATA flash disk controller
operations. This bit is cleared at power up and remains cleared until the ATA flash disk
controller is ready to accept a command.
DWF
This bit, if set, indicates a write fault has occurred.
DSC
This bit is set when the ATA flash disk controller is ready.
DRQ
The Data Request is set when the ATA flash disk controller requires that information be
transferred either to or from the host through the Data register.
CORR
This bit is set when a Correctable data error has been encountered and the data has
been corrected. This condition does not terminate a multi-sector Read operation.
ERR
This bit is set when the previous command has ended in some type of error. The bits in
the Error register contain additional information describing the error. It is recommended
that media access commands (such as Read-Sectors and Write-Sectors) that end with
an error condition should have the address of the first sector in error in the command
block registers.
10.1.2.10 Device Control Register (Write Only) (See Table 10-1 for register addressing)
This register is used to control the ATA flash disk controller interrupt request and to issue a software Reset. This
register can be written to even if the device is BUSY. The bits are defined as follows:
Symbol
Function
SW Rst
This bit is set to 1 in order to force the ATA flash disk controller to perform a software
Reset operation. The chip remains in Reset until this bit is reset to ‘0.’
-IEn
0: The Interrupt Enable bit enables interrupts
1: Interrupts from the ATA flash disk controller are disabled
This bit is set to 1 at Power-On and Reset.
D7
D6
D5
D4
D3
D2
D1
D0
Reset Value
BUSY
RDY
DWF
DSC
DRQ
CORR
0
ERR
1000 0000b
D7
D6
D5
D4
D3
D2
D1
D0
Reset Value
XXX
X
1
SW Rst
-IEn
0
0000 1010b
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